Abstract: A memory device includes a memory array and a peripheral circuit coupled to the memory array. The memory array includes a first memory cell and a second memory cell coupled to a same bit line and being adjacent. The peripheral circuit includes a page buffer circuit. The page buffer circuit includes: a sensing node coupled to the bit line; a first latch circuit coupled to the sensing node, and configured to latch a programmed state of first memory cell; a charge and discharge circuit coupled to the sensing node, and configured to: charge the sensing node, and discharge the sensing node, wherein discharge duration of the sensing node is related to the programmed state; and a second latch circuit coupled to the sensing node, and configured to latch, according to a voltage value of the sensing node after the discharge duration, information of whether second memory cell passes program verification.

Abstract: This application discloses a cryopump, including a pump housing, a radiation shield in the pump housing, a first-stage cold storage component in the pump housing, a second-stage cold storage component in the holding space of the radiation shield, a connector connecting the first-stage cold storage component and the radiation shield, and a cryopanel assembly in the holding space and connected to the second-stage cold storage component.

Abstract: A memory device includes an array of memory cells and a peripheral circuit coupled to the array of memory cells. The array of memory cells includes a first memory cell and a second memory cell. Each of the first and second memory cells is configured to store N-bits data. The peripheral circuit includes a page buffer circuit and control logic. The page buffer circuit includes at least a page buffer circuit coupled to the first and second memory cells, respectively. The page buffer circuit includes a sense out (SO) node and a cache storage unit.

Abstract: Examples of the present application provide a memory, an operation method thereof and a memory system, and relate to, but are not limited to, the field of storage technology. The memory includes a peripheral circuit, a plurality of word lines and a plurality of rows of memory cells. Each row of the memory cells is coupled with one word line. The peripheral circuit is configured to apply a first voltage to a first word line of the plurality of word lines in each of a plurality of first time periods. A second voltage is applied to the first word line in a second time period between every two adjacent ones of the plurality of first time periods, wherein the second voltage is configured to turn on the memory cells coupled with the first word line. As such, the accuracy of data reading can be improved.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for operating a memory device having multiple storage modes. In one example method, a portion of a memory array is selected, wherein the portion of the memory array is programmable in a first storage mode or a second storage mode. The second storage mode has a lower storage density than the first storage mode, and the first storage mode corresponds to a first erase operation. A switch erase operation is performed to switch the portion of the memory array from the first storage mode to a switched second storage mode, wherein the switched second storage mode has the same storage density as the second storage mode and corresponds to the switch erase operation. The switch erase operation is different from the first erase operation on the memory array in the first storage mode.

Abstract: In certain aspects, a memory device includes an array of memory cells, including a first memory cell and a second memory cell, and a peripheral circuit. The peripheral circuit includes a page buffer circuit and control logic. The control logic is configured to suspend a program operation on the first memory cell responsive to receiving a suspension command indicative of executing a read operation on the second memory cell, control the page buffer circuit to release a sensing storage unit and a cache storage unit of the page buffer circuit from being occupied by a suspension of the program operation through a usage of a dynamic storage unit of the page buffer circuit during the suspension of the program operation, and initiate a read operation on the second memory cell using the sensing storage unit and the cache storage unit.

Abstract: In certain aspects, a memory device includes an array of memory cells and a peripheral circuit. The array of memory cells includes a first memory cell and a second memory cell. The peripheral circuit includes a page buffer circuit and control logic. The page buffer circuit is coupled to the first and second memory cells, respectively, and includes a sense out (SO) node and a cache storage unit. The control logic is coupled to the page buffer and configured to suspend a program operation on the first memory cell responsive to receiving a suspension command indicative of executing a read operation on the second memory cell. The control logic is further configured to control the page buffer circuit to store suspended program information associated with a suspension of the program operation, and initiate the read operation on the second memory cell through the SO node and the cache storage unit.

Abstract: In certain aspects, a memory device includes N memory planes, where N is an integer greater than 1, M asynchronous multi-plane independent (AMPI) read units, each coupled to one of the N memory planes, where M is an integer smaller than or equal to N, a first microcontroller unit (MCU) coupled to each memory plane of the N memory planes, and a multiplexing circuit coupled to the N memory planes, the first MCU, and the M AMPI read units.

Abstract: A memory device includes N memory planes (N is an integer greater than 1), M asynchronous multi-plane independent (AMPI) read units (M is an integer smaller than or equal to N), a first microcontroller unit (MCU), and a multiplexing circuit coupled to the N memory planes, the first MCU, and the M AMPI read units. Each AMPI read unit is configured to provide an AMPI read control signal for a respective memory plane to control an AMPI read operation on the respective memory plane. The first MCU is configured to provide a non-AMPI read control signal for each memory plane to control a non-AMPI read operation on each memory plane. The multiplexing circuit is configured to, in a non-AMPI read operation, direct a non-AMPI read control signal to each memory plane from the first MCU, and in an AMPI read operation, direct each AMPI read control signal of M AMPI read control signals to the respective memory plane from the corresponding AMPI read unit.

Abstract: In certain aspects, a memory device includes an array of memory cells, including a first memory cell and a second memory cell, and a peripheral circuit. The peripheral circuit includes a page buffer circuit and control logic. The control logic is configured to suspend a program operation on the first memory cell responsive to receiving a suspension command, control the page buffer circuit to store suspended program information associated with a suspension of the program operation, control the page buffer circuit to release a sensing storage unit and a cache storage unit of the page buffer circuit from being occupied by the suspension of the program operation through a storage of a piece of program information from the suspended program information in a memory controller, and initiate a read operation on the second memory cell using the sensing storage unit and the cache storage unit.

Abstract: A memory device includes an array of memory cells columns and rows, word lines respectively coupled to rows of the memory cells, bit lines respectively coupled to the columns of the memory cells, and a peripheral circuit coupled to the array of memory cells through the bit and word lines and including page buffer circuits respectively coupled to the bit lines. Each page buffer circuit includes one cache storage unit configured to, in programming a select row based on a current data page, sequentially store each of N bits of the current data page and each of the N bits of a next data page, N?1 data storage units each configured to, in programming the select row based on the current data page, store a respective one of the N bits of the current data page and a respective one of the N bits of the next data page in a time division manner, and a multipurpose storage unit configured to, in programming the select row based on the current data page, store at least one of the N bits of the current data page.

Abstract: In certain aspects, a memory device includes an array of memory cells columns and rows, word lines respectively coupled to rows of the memory cells, bit lines respectively coupled to the columns of the memory cells, and a peripheral circuit coupled to the array of memory cells through the bit lines and the word lines and configured to program a select row of the rows of the memory cells based on a current data page. Each memory cell is set to one of 2N levels corresponding a piece of N-bits data, where N is an integer greater than 2. The peripheral circuit includes page buffer circuits respectively coupled to the bit lines. Each page buffer circuit includes one cache storage unit, N?1 data storage units, and a multipurpose storage unit. The cache storage unit is configured to sequentially receive N bits of the current data page and N bits of a next data page, and sequentially store one of the N bits of the current data page and each of the N bits of the next data page.

Abstract: In certain aspects, a memory device includes a plurality of memory cells and a peripheral circuit coupled to the plurality of memory cells. The peripheral circuit includes a page buffer, which includes a page buffer circuit and control logic coupled to the page buffer circuit. The page buffer circuit includes a dynamic storage unit and a first non-dynamic storage unit. The control logic is configured to determine whether an information swapping process is performed between the dynamic storage unit and the first non-dynamic storage unit based on a type of an operation to be performed on the page buffer circuit and an information storage manner between the dynamic storage unit and the first non-dynamic storage unit. The control logic is further configured to perform the operation on the page buffer circuit based on the determining whether the information swapping process is performed.

Abstract: In certain aspects, a memory device includes an array of memory cells columns and rows, word lines respectively coupled to rows of the memory cells, bit lines respectively coupled to the columns of the memory cells, and a peripheral circuit coupled to the array of memory cells through the bit lines and the word lines and configured to program a select row of the rows of the memory cells based on a current data page. Each memory cell is set to one of 2N levels corresponding a piece of N-bits data, where N is an integer greater than 2. The peripheral circuit includes page buffer circuits respectively coupled to the bit lines. Each page buffer circuit includes one cache storage unit, N?1 data storage units, and a multipurpose storage unit. The cache storage unit is configured to sequentially receive N bits of the current data page and N bits of a next data page, and sequentially store one of the N bits of the current data page and each of the N bits of the next data page.

Abstract: In certain aspects, a memory device includes an array of memory cells and a peripheral circuit. The array of memory cells includes a first memory cell and a second memory cell. The peripheral circuit includes a page buffer circuit and control logic. The page buffer circuit is coupled to the first and second memory cells, respectively, and includes a sense out (SO) node and a cache storage unit. The control logic is coupled to the page buffer and configured to suspend a program operation on the first memory cell responsive to receiving a suspension command indicative of executing a read operation on the second memory cell. The control logic is further configured to control the page buffer circuit to store suspended program information associated with a suspension of the program operation, and initiate the read operation on the second memory cell through the SO node and the cache storage unit.

Abstract: In certain aspects, a memory device includes an array of memory cells, including a first memory cell and a second memory cell, and a peripheral circuit. The peripheral circuit includes a page buffer circuit and control logic. The control logic is configured to suspend a program operation on the first memory cell responsive to receiving a suspension command, control the page buffer circuit to store suspended program information associated with a suspension of the program operation, control the page buffer circuit to release a sensing storage unit and a cache storage unit of the page buffer circuit from being occupied by the suspension of the program operation through a storage of a piece of program information from the suspended program information in a memory controller, and initiate a read operation on the second memory cell using the sensing storage unit and the cache storage unit.

Abstract: In certain aspects, a memory device includes an array of memory cells, including a first memory cell and a second memory cell, and a peripheral circuit. The peripheral circuit includes a page buffer circuit and control logic. The control logic is configured to suspend a program operation on the first memory cell responsive to receiving a suspension command indicative of executing a read operation on the second memory cell, control the page buffer circuit to release a sensing storage unit and a cache storage unit of the page buffer circuit from being occupied by a suspension of the program operation through a usage of a dynamic storage unit of the page buffer circuit during the suspension of the program operation, and initiate a read operation on the second memory cell using the sensing storage unit and the cache storage unit.

Abstract: A memory device includes a plurality of planes. A method of programming the memory device includes applying a first program pulse to one or more memory cells of a first plane of the plurality of planes, verifying whether each one of the memory cells reaches a predetermined program state, and in response to a preset number of the memory cells in the first plane failing to reach the predetermined program state after the memory cells being verified for a predetermined number of times, bypassing the first plane when applying a second program pulse after the first program pulse.

Abstract: A memory device includes N memory planes (N is an integer greater than 1), M asynchronous multi-plane independent (AMPI) read units (M is an integer smaller than or equal to N), a first microcontroller unit (MCU), and a multiplexing circuit coupled to the N memory planes, the first MCU, and the M AMPI read units. Each AMPI read unit is configured to provide an AMPI read control signal for a respective memory plane to control an AMPI read operation on the respective memory plane. The first MCU is configured to provide a non-AMPI read control signal for each memory plane to control a non-AMPI read operation on each memory plane. The multiplexing circuit is configured to, in a non-AMPI read operation, direct a non-AMPI read control signal to each memory plane from the first MCU, and in an AMPI read operation, direct each AMPI read control signal of M AMPI read control signals to the respective memory plane from the corresponding AMPI read unit.

Abstract: A memory device includes a plurality of planes. A method of programming the memory device includes applying a first program pulse to one or more memory cells of a first plane of the plurality of planes, verifying whether each one of the memory cells reaches a predetermined program state, and in response to a preset number of the memory cells in the first plane failing to reach the predetermined program state after the memory cells being verified for a predetermined number of times, bypassing the first plane when applying a second program pulse after the first program pulse.