Patents by Inventor Jialiang LIU

Jialiang LIU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12265987
    Abstract: Methods, systems, and computer programs are presented for eliminating bias while training an ML model using training data that includes past experimental data. One method includes accessing experiment results, for A/B testing of a first model, that comprise information regarding engagement with a first set of items presented to users, each item being presented within an ordered list of results. A position bias is calculated for positions within the ordered list of results where the items were presented. A machine-learning program is trained to obtain a second model using a training set comprising values for features that include the calculated position bias. The method includes detecting a second set of items to be ranked for presentation to a first user, and calculates, using the second model, a relevance score for the second set of items, which are ranked based on the respective relevance score and presented on a display.
    Type: Grant
    Filed: October 28, 2022
    Date of Patent: April 1, 2025
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Jialiang Mao, Rina Siller Friedberg, Karthik Rajkumar, Qian Yao, Min Liu, YinYin Yu
  • Publication number: 20250101006
    Abstract: The invention provides a novel process, novel process steps and novel intermediates useful in the synthesis of pharmaceutically active compounds, especially KRAS G12C inhibitors. The present invention provides a direct enantioselective chemical manufacturing method of making Compound A, or a pharmaceutically acceptable hydrate or solvent thereof: (I). The invention provides a process for preparing Intermediate B6* comprising reacting Intermediate B4* with Intermediate B5* in an atroposelective coupling reaction, using a chiral catalyst.
    Type: Application
    Filed: January 30, 2023
    Publication date: March 27, 2025
    Inventors: Markus BAENZIGER, Fabrice GALLOU, Fengfeng GUO, Rudolf HÄNGGI, Enjian HAN, Guido JORDINE, Jialiang LI, Weipeng LIU, Bukeyan MIAO, Shaofeng RONG, Ernesto SANTANDREA, Paul Bernd SCHIRNER, Xiaodong SHEN, Can WANG, Hao ZHANG
  • Patent number: 12237474
    Abstract: Molten lithium electrochemical cells are disclosed. A solid electrolyte separates a molten lithium metal or molten lithium metal alloy from a cathode. The molten lithium cells provide high Coulombic efficiency and energy efficiency at operating temperatures less than 600° C. The cells are useful for stationary energy storage in power grids.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: February 25, 2025
    Assignee: MetaGenesis, Ltd.
    Inventors: Yang Jin, Kai Liu, Jialiang Lang
  • Patent number: 12219371
    Abstract: A method and system for networking of spliced building blocks, and the spliced building blocks applicable to wireless networking are provided.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: February 4, 2025
    Assignee: SHANGHAI BLOKS TECHNOLOGY GROUP CO., LTD.
    Inventors: Jialiang Zhao, Chao Gao, Ye Xiao, Shanjun Deng, Song Liu, Chang Liu, Shanjun Li, Chenlu Liu
  • Publication number: 20250028453
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for operating a memory device having multiple storage modes. In one example method, a portion of a memory array is selected, wherein the portion of the memory array is programmable in a first storage mode or a second storage mode. The second storage mode has a lower storage density than the first storage mode, and the first storage mode corresponds to a first erase operation. A switch erase operation is performed to switch the portion of the memory array from the first storage mode to a switched second storage mode, wherein the switched second storage mode has the same storage density as the second storage mode and corresponds to the switch erase operation. The switch erase operation is different from the first erase operation on the memory array in the first storage mode.
    Type: Application
    Filed: August 17, 2023
    Publication date: January 23, 2025
    Inventors: Yi Zhang, Lei Guan, Hongtao Liu, Xiaojiang Guo, Chenhui Li, Jialiang Deng, Zhenjia Chen
  • Publication number: 20230387342
    Abstract: The disclosure provides a method for preparing an electrode film layer on a surface of a solar cell substrate. The method includes: a) obtaining a metal electrode material melt by heating and melting a metal electrode material under a vacuum condition; b) bombarding the metal electrode material melt with an ion source at low energy, so that it is sputtered and deposited on the surface of the solar cell substrate to form the electrode film layer; in which the energy of low energy bombarding is 30 eV to 80 eV.
    Type: Application
    Filed: August 14, 2023
    Publication date: November 30, 2023
    Inventors: Ping Xiao, Jiguang Xiong, Zhiguo Zhao, Jialiang Liu, Mengjie Li, Dongming Zhao, Xiaojun Qin, Yun Zhang, Chao Dong, Xueling Wang, Shisen Xu, Ruwei Liu, Sichao Liang
  • Patent number: 9686553
    Abstract: An advanced video coding and decoding chip and a method with an optimized processing sequence for the sub-blocks, each including 4×4 pixels, of a macroblock in a discrete cosine transform (DCT) and an inverse DCT are disclosed, wherein the compression hardware and the reconstruction hardware execute the compression and the reconstruction of at least part of a field in parallel.
    Type: Grant
    Filed: March 6, 2015
    Date of Patent: June 20, 2017
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
    Inventors: ChuanChuan Zhu, Jialiang Liu, Zixi Wang, Jin Shao
  • Publication number: 20160173876
    Abstract: An advanced video coding and decoding chip and a method with an optimized processing sequence for the sub-blocks, each including 4×4 pixels, of a macroblock in a discrete cosine transform (DCT) and an inverse DCT are disclosed, wherein the compression hardware and the reconstruction hardware execute the compression and the reconstruction of at least part of a field in parallel.
    Type: Application
    Filed: March 6, 2015
    Publication date: June 16, 2016
    Inventors: ChuanChuan ZHU, Jialiang LIU, Zixi WANG, Jin SHAO