Patents by Inventor Jialin Weng

Jialin Weng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated circuits and methods of forming integrated circuits with interlayer dielectric protection
    Patent number: 9123783
    Abstract: Integrated circuits and methods of forming integrated circuits are provided herein. In an embodiment, a method of forming an integrated circuit includes providing a base substrate having an embedded electrical contact disposed therein. An interlayer dielectric is formed overlying the base substrate, and a recess is etched through the interlayer dielectric over the embedded electrical contact. A protecting liner is formed in the recess and over an exposed surface of the embedded electrical contact in the recess. The protecting liner includes at least two liner layers that have materially different etch rates in different etchants. A portion of the protecting liner is removed over the surface of the embedded electrical contact to again expose the surface of the embedded electrical contact in the recess. An embedded electrical interconnect is formed in the recess. The embedded electrical interconnect overlies the protecting liner on sides of the recess.
    Type: Grant
    Filed: November 9, 2012
    Date of Patent: September 1, 2015
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Xin Wang, Changyong Xiao, Yue Hu, Yong Meng Lee, Meng Luo, Jialin Weng, Wei Hua Tong, Wen-Pin Peng
  • INTEGRATED CIRCUITS AND METHODS OF FORMING INTEGRATED CIRCUITS WITH INTERLAYER DIELECTRIC PROTECTION
    Publication number: 20140131881
    Abstract: Integrated circuits and methods of forming integrated circuits are provided herein. In an embodiment, a method of forming an integrated circuit includes providing a base substrate having an embedded electrical contact disposed therein. An interlayer dielectric is formed overlying the base substrate, and a recess is etched through the interlayer dielectric over the embedded electrical contact. A protecting liner is formed in the recess and over an exposed surface of the embedded electrical contact in the recess. The protecting liner includes at least two liner layers that have materially different etch rates in different etchants. A portion of the protecting liner is removed over the surface of the embedded electrical contact to again expose the surface of the embedded electrical contact in the recess. An embedded electrical interconnect is formed in the recess. The embedded electrical interconnect overlies the protecting liner on sides of the recess.
    Type: Application
    Filed: November 9, 2012
    Publication date: May 15, 2014
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Xin Wang, Changyong Xiao, Yue Hu, Yong Meng Lee, Meng Luo, Jialin Weng, Wei Hua Tong, Wen-Pin Peng