Abstract: The present invention relates to a glass substrate provided with a stack of thin coating layers formed by a first layer of anti-reflective dielectric material, with a refractive index of 1.65 to 2.65, located above the glass substrate. At least one structure of two layers formed by a first layer of an anti-reflective transparent dielectric material with a refractive index of 1.32 to 1.55, located in the bottom position, and a second layer of a metal functional layer with reflective properties in the infrared range, located in the top position, said structure being located above the first layer of anti-reflective dielectric material. A second layer of absorbent material forming an anti-corrosion barrier for protecting the metal functional layer against oxidation and corrosion. A third layer of an anti-reflective material, said layer being selected from a metal oxide with a refractive index of 1.32 to 1.55, a metal oxide with a refractive index of 1.65 to 1.

Abstract: An isolation circuit includes a first multiplexer, a D flip-flop, a second multiplexer, an OR gate, and an AND gate. The first multiplexer selects a data signal or a scan-in signal as a first element output signal according to a scan enable signal. The D flip-flop generates a second element output signal according to the first element output signal. The second element output signal is fed back to the first multiplexer and is used as the data signal. The second multiplexer selects an isolation signal or the second element output signal as a third element output signal according to a test enable signal. The OR gate generates a fourth element output signal according to the scan enable signal and the third element output signal. The AND gate generates a second power domain signal according to a first power domain signal and the fourth element output signal.

Abstract: An isolation circuit includes a first multiplexer, a D flip-flop, a second multiplexer, an OR gate, and an AND gate. The first multiplexer selects a data signal or a scan-in signal as a first element output signal according to a scan enable signal. The D flip-flop generates a second element output signal according to the first element output signal. The second element output signal is fed back to the first multiplexer and is used as the data signal. The second multiplexer selects an isolation signal or the second element output signal as a third element output signal according to a test enable signal. The OR gate generates a fourth element output signal according to the scan enable signal and the third element output signal. The AND gate generates a second power domain signal according to a first power domain signal and the fourth element output signal.