Patents by Inventor Jiamiao Tang

Jiamiao Tang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9837340
    Abstract: Some embodiments of the invention include a connecting structure between a support and at least one die attached to the support. The die includes a number of die bond pads on a surface of the die. The connecting structure includes a plurality of via and groove combinations. Conductive material is formed in the via and groove combinations to provide connection between the die bond pads and bond pads on the support. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: December 5, 2017
    Assignee: Intel Corporation
    Inventors: Jiamiao Tang, Henry Xu, Shinichi Sakamoto
  • Patent number: 9778688
    Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package. In embodiments, an integrated circuit (IC) package may include a flexible substrate. The flexible substrate may have a plurality of dies coupled therewith. The IC package may include a first encapsulation material, having a first rigidity, disposed on the flexible substrate to at least partially encapsulate each die of the plurality dies. The IC package may further include a second encapsulation material, having a second rigidity, disposed on the flexible substrate. In embodiments, the second rigidity and the first rigidity are different from one another. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: November 12, 2014
    Date of Patent: October 3, 2017
    Assignee: INTEL CORPORATION
    Inventors: Jiamiao Tang, Junfeng Zhao, Michael P. Skinner, Yong She, Jiun Hann Sir, Bok Eng Cheah, Shanggar Periaman, Kooi Chi Ooi, Yen Hsiang Chew
  • Publication number: 20160379920
    Abstract: Some embodiments of the invention include a connecting structure between a support and at least one die attached to the support. The die includes a number of die bond pads on a surface of the die, The connecting structure includes a plurality of via and groove combinations. Conductive material is formed in the via and groove combinations to provide connection between the die bond pads and bond pads on the support. Other embodiments are described and claimed.
    Type: Application
    Filed: June 28, 2016
    Publication date: December 29, 2016
    Inventors: Jiamiao Tang, Henry Xu, Shinichi Sakamoto
  • Publication number: 20160324487
    Abstract: Embodiments described herein may fully integrate personal computing and health care into a wearable waistband having a length sensor, a pressure sensor, and a motion sensor; or into a wearable “mesh” having an array of sound sensors, which will create convenient and seamless access to a personal computer and biofeedback of the wearer. Such biofeedback from the waistband may include determining respiration rate, waist length, food quantity of a meal, sitting or sleep time, and frequency of visits to the bathroom. Such biofeedback from the mesh or array may include determining whether there is or has been damage or other issues of the heart, lungs, bones, joints, jaw, throat, arteries, digestive tract, and the like. Such biofeedback may also detect whether whether a person has an allergic reaction at a location, is drinking (and what volume of fluid), is walking, is jogging or is running.
    Type: Application
    Filed: November 27, 2014
    Publication date: November 10, 2016
    Inventors: Mao GUO, Junfeng ZHAO, Michael P. SKINNER, Ke XIAO, Jiamiao TANG, Bin LIU, Li DENG
  • Publication number: 20160327977
    Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package. In embodiments, an integrated circuit (IC) package may include a flexible substrate. The flexible substrate may have a plurality of dies coupled therewith. The IC package may include a first encapsulation material, having a first rigidity, disposed on the flexible substrate to at least partially encapsulate each die of the plurality dies. The IC package may further include a second encapsulation material, having a second rigidity, disposed on the flexible substrate. In embodiments, the second rigidity and the first rigidity are different from one another. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: November 12, 2014
    Publication date: November 10, 2016
    Inventors: Jiamiao Tang, Junfeng Zhao, Michael P. Skinner, Yong She, Jiun Hann Sir, Bok Eng Cheah, Shanggar Periaman, Kooi Chi Ooi, Yen Hsiang Chew
  • Patent number: 9385094
    Abstract: Some embodiments of the invention include a connecting structure between a support and at least one die attached to the support. The die includes a number of die bond pads on a surface of the die. The connecting structure includes a plurality of via and groove combinations. Conductive material is formed in the via and groove combinations to provide connection between the die bond pads and bond pads on the support. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 16, 2015
    Date of Patent: July 5, 2016
    Assignee: Intel Corporation
    Inventors: Jiamiao Tang, Henry Xu, Shinichi Sakamoto
  • Publication number: 20150187713
    Abstract: Some embodiments of the invention include a connecting structure between a support and at least one die attached to the support. The die includes a number of die bond pads on a surface of the die. The connecting structure includes a plurality of via and groove combinations. Conductive material is formed in the via and groove combinations to provide connection between the die bond pads and bond pads on the support. Other embodiments are described and claimed.
    Type: Application
    Filed: March 16, 2015
    Publication date: July 2, 2015
    Inventors: Jiamiao Tang, Henry Xu, Shinichi Sakamoto
  • Patent number: 8981573
    Abstract: Some embodiments of the invention include a connecting structure between a support and at least one die attached to the support. The die includes a number of die bond pads on a surface of the die. The connecting structure includes a plurality of via and groove combinations. Conductive material is formed in the via and groove combinations to provide connection between the die bond pads and bond pads on the support. Other embodiments are described and claimed.
    Type: Grant
    Filed: August 19, 2013
    Date of Patent: March 17, 2015
    Assignee: Intel Corporation
    Inventors: Jiamiao Tang, Henry Xu, Shinichi Sakamoto
  • Patent number: 8963333
    Abstract: Some embodiments of the invention include a connecting structure between a support and at least one die attached to the support. The die includes a number of die bond pads on a surface of the die. The connecting structure includes a plurality of via and groove combinations. Conductive material is formed in the via and groove combinations to provide connection between the die bond pads and bond pads on the support. Other embodiments are described and claimed.
    Type: Grant
    Filed: August 19, 2013
    Date of Patent: February 24, 2015
    Assignee: Intel Corporation
    Inventors: Jiamiao Tang, Henry Xu, Shinichi Sakamoto
  • Publication number: 20140042639
    Abstract: Some embodiments of the invention include a connecting structure between a support and at least one die attached to the support. The die includes a number of die bond pads on a surface of the die. The connecting structure includes a plurality of via and groove combinations. Conductive material is formed in the via and groove combinations to provide connection between the die bond pads and bond pads on the support. Other embodiments are described and claimed.
    Type: Application
    Filed: August 19, 2013
    Publication date: February 13, 2014
    Inventors: Jiamiao Tang, Henry Xu, Shinichi Sakamoto
  • Publication number: 20130334707
    Abstract: Some embodiments of the invention include a connecting structure between a support and at least one die attached to the support. The die includes a number of die bond pads on a surface of the die. The connecting structure includes a plurality of via and groove combinations. Conductive material is formed in the via and groove combinations to provide connection between the die bond pads and bond pads on the support. Other embodiments are described and claimed.
    Type: Application
    Filed: August 19, 2013
    Publication date: December 19, 2013
    Inventors: Jiamiao Tang, Henry Xu, Shinichi Sakamoto
  • Patent number: 8513108
    Abstract: Some embodiments of the invention include a connecting structure between a support and at least one die attached to the support. The die includes a number of die bond pads on a surface of the die. The connecting structure includes a plurality of via and groove combinations. Conductive material is formed in the via and groove combinations to provide connection between the die bond pads and bond pads on the support. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: August 20, 2013
    Assignee: Intel Corporation
    Inventors: Jiamiao Tang, Henry Xu, Shinichi Sakamoto
  • Publication number: 20120108053
    Abstract: Some embodiments of the invention include a connecting structure between a support and at least one die attached to the support. The die includes a number of die bond pads on a surface of the die. The connecting structure includes a plurality of via and groove combinations. Conductive material is formed in the via and groove combinations to provide connection between the die bond pads and bond pads on the support. Other embodiments are described and claimed.
    Type: Application
    Filed: December 22, 2011
    Publication date: May 3, 2012
    Inventors: Jiamiao Tang, Henry Xu, Shinichi Sakamoto
  • Patent number: 8084867
    Abstract: Some embodiments of the invention include a connecting structure between a support and at least one die attached to the support. The die includes a number of die bond pads on a surface of the die. The connecting structure includes a plurality of via and groove combinations. Conductive material is formed in the via and groove combinations to provide connection between the die bond pads and bond pads on the support. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 29, 2006
    Date of Patent: December 27, 2011
    Assignee: Intel Corporation
    Inventors: Jiamiao Tang, Henry Xu, Shinichi Sakamoto
  • Publication number: 20100244268
    Abstract: Some embodiments of the invention include a connecting structure between a support and at least one die attached to the support. The die includes a number of die bond pads on a surface of the die. The connecting structure includes a plurality of via and groove combinations. Conductive material is formed in the via and groove combinations to provide connection between the die bond pads and bond pads on the support. Other embodiments are described and claimed.
    Type: Application
    Filed: June 29, 2006
    Publication date: September 30, 2010
    Inventors: Jiamiao Tang, Henry Xu, Shinichi Sakamoto
  • Patent number: 7723164
    Abstract: A process includes mating a first heat spreader and a second heat spreader, such that the first heat spreader at a mating surface and second heat spreader at a mating surface become parallel and adjacent. The process includes placing a first die in a first die recess of the first heat spreader, and placing a second die in a second die recess in the second heat spreader. The process includes reflowing thermal interface material between each die and respective heat spreader. Thereafter, the process includes separating the first heat spreader and the second heat spreader. A package is achieved by the process, with reduced thicknesses. The package can be disposed onto a mounting substrate. The package can be assembled into a computing system.
    Type: Grant
    Filed: September 1, 2006
    Date of Patent: May 25, 2010
    Assignee: Intel Corporation
    Inventors: Daoqiang Lu, Jiangqi He, Xiang Yin Zeng, Jiamiao Tang
  • Patent number: 7659143
    Abstract: A method includes mating a first heat spreader and a second heat spreader, such that the first heat spreader at a mating surface and second heat spreader at a mating surface become parallel and adjacent. The mated first heat spreader and second heat spreader have at least one convection channel disposed therebetween. A process includes placing a first die in a first die recess of the first heat spreader, and placing a second die on a second die site on the second heat spreader. The process includes reflowing thermal interface material between each die and respective heat spreader. A package is achieved by the method, with reduced thicknesses. The package can be coupled through a bumpless build-up layer. The package can be assembled into a computing system.
    Type: Grant
    Filed: September 29, 2006
    Date of Patent: February 9, 2010
    Assignee: Intel Corporation
    Inventors: Jiamiao Tang, Daoqiang Lu, Jiangqi He, Xiang Yin Zeng
  • Patent number: 7535689
    Abstract: An integrated circuit with reduced pad capacitance, having a trench formed in the silicon substrate below the pad to reduce the pad capacitance. In another embodiment, an encapsulated air cavity is formed underneath the pad.
    Type: Grant
    Filed: June 21, 2007
    Date of Patent: May 19, 2009
    Assignee: Intel Corporation
    Inventors: Xiang Yin Zeng, Ming Dong Cui, Gregory V. Christensen, Mostafa Naguib Abdulla, Daoqiang Lu, Jiangqi He, Jiamiao Tang
  • Publication number: 20090079064
    Abstract: Methods of forming microelectronic device structures are described. Those methods may include placing a plurality of support rings onto a tacky layer of a support carrier, wherein the support rings are disposed within a cavity of the support carrier; placing a plurality of thin die onto a pedestal of the support carrier, wherein a top surface of the thin die is substantially flush with at top surface of the support ring; and then building up layers on the top surface of the die.
    Type: Application
    Filed: September 25, 2007
    Publication date: March 26, 2009
    Inventors: Jiamiao Tang, Daoqiang Lu, Rougang Zhao
  • Publication number: 20080316662
    Abstract: An integrated circuit with reduced pad capacitance, having a trench formed in the silicon substrate below the pad to reduce the pad capacitance. In another embodiment, an encapsulated air cavity if formed underneath the pad. Other embodiments are described and claimed.
    Type: Application
    Filed: June 21, 2007
    Publication date: December 25, 2008
    Inventors: Xiang Yin Zeng, Ming Dong Cui, Gregory V. Christensen, Mostafa Naguib Abdulla, Daoqiang Lu, Jiangqi He, Jiamiao Tang