Patents by Inventor Jiamin Situ

Jiamin Situ has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11609599
    Abstract: An electronic device comprises a first processor, a second processor and a communication interface. The first processor operates according to a first clock, and comprises a first time-stamp counter to count the first clock to obtain a first count value. The second processor operates according to a second clock, and comprises a second time-stamp counter to count the second clock to obtain a second count value. The communication interface is coupled between the first processor and the second processor. The first processor periodically sends the first count value to the second processor through the communication interface. When the second processor receives the first count value, the second processor adds a preset deviation value to the first count value to obtain a synchronization value, resets the second count value, and the sum of the synchronization value and the second count value is read by the second processor.
    Type: Grant
    Filed: October 25, 2021
    Date of Patent: March 21, 2023
    Assignee: SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.
    Inventors: Jiamin Situ, Zhenhua Huang, Yang Shi, Jun Wu
  • Publication number: 20220137661
    Abstract: An electronic device comprises a first processor, a second processor and a communication interface. The first processor operates according to a first clock, and comprises a first time-stamp counter to count the first clock to obtain a first count value. The second processor operates according to a second clock, and comprises a second time-stamp counter to count the second clock to obtain a second count value. The communication interface is coupled between the first processor and the second processor. The first processor periodically sends the first count value to the second processor through the communication interface. When the second processor receives the first count value, the second processor adds a preset deviation value to the first count value to obtain a synchronization value, resets the second count value, and the sum of the synchronization value and the second count value is read by the second processor.
    Type: Application
    Filed: October 25, 2021
    Publication date: May 5, 2022
    Inventors: Jiamin SITU, Zhenhua HUANG, Yang SHI, Jun WU
  • Patent number: 10862508
    Abstract: A method for encoding and compressing a bit stream is provided. The method includes: receiving a bit stream; determining whether a first number of bits that are consecutive and identical in the bit stream is greater than or equal to a first preset value; and when the first number is greater than or equal to the first preset value, the first number of bits are encoded as a first code in a first encoding way, wherein the first code is composed of a first prefix and a first suffix, and the first prefix represents what the consecutive bits are and the first suffix represents the first number.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: December 8, 2020
    Assignee: SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.
    Inventors: Wei Zhao, Zongpu Qi, Zheng Wang, Jiamin Situ