Patents by Inventor Jian-Bin Shiu

Jian-Bin Shiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9761791
    Abstract: A structure of a conductive pad is provided. The structure includes a first conductive layer. A first dielectric layer covers the first conductive layer. A first contact hole is disposed within the first dielectric layer. A second conductive layer fills in the first conductive hole and extends from the first conductive hole to a top surface of the first dielectric layer so that the second conductive layer forms a step profile. A second dielectric layer covers the first dielectric layer and the second conductive layer. A third conductive layer contacts and covers the step profile.
    Type: Grant
    Filed: July 8, 2014
    Date of Patent: September 12, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Jian-Bin Shiu, Tung-Sheng Lee
  • Patent number: 9728567
    Abstract: A semiconductor sensor device is disclosed. The semiconductor sensor device includes a plurality of pixels and a phase grating structure. The phase grating structure has periodically arranged patterns and is disposed on the pixels.
    Type: Grant
    Filed: December 2, 2013
    Date of Patent: August 8, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Jian-Bin Shiu, Wen-Zheng Yu
  • Patent number: 9536831
    Abstract: A semiconductor device is disclosed. The semiconductor device includes: a substrate having a die region and a scribe line region defined thereon; and a bonding pad on the die region of the substrate and overlapping the scribe line region.
    Type: Grant
    Filed: July 2, 2015
    Date of Patent: January 3, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Jian-Bin Shiu
  • Publication number: 20160336265
    Abstract: A semiconductor device is disclosed. The semiconductor device includes: a substrate having a die region and a scribe line region defined thereon; and a bonding pad on the die region of the substrate and overlapping the scribe line region.
    Type: Application
    Filed: July 2, 2015
    Publication date: November 17, 2016
    Inventor: Jian-Bin Shiu
  • Publication number: 20150349242
    Abstract: A structure of a conductive pad is provided. The structure includes a first conductive layer. A first dielectric layer covers the first conductive layer. A first contact hole is disposed within the first dielectric layer. A second conductive layer fills in the first conductive hole and extends from the first conductive hole to a top surface of the first dielectric layer so that the second conductive layer forms a step profile. A second dielectric layer covers the first dielectric layer and the second conductive layer. A third conductive layer contacts and covers the step profile.
    Type: Application
    Filed: July 8, 2014
    Publication date: December 3, 2015
    Inventors: Jian-Bin Shiu, Tung-Sheng Lee
  • Patent number: 9070652
    Abstract: A monitoring method of a semiconductor process includes the following steps. A semiconductor substrate is provided, and a test structure is formed thereon. The method of forming the test structure includes the following steps. A first doped region and a second doped region are formed in the semiconductor substrate, and an insulating layer is formed on the semiconductor substrate. Subsequently, a conductive layer is directly formed on the insulating layer to complete the formation of the test structure, in which the conductive layer in a floating state partially overlaps the first doped region and partially overlaps the second doped region. Then, a voltage signal is applied to the test structure and the breakdown voltage (Vbd) between the first doped region and the second doped region is measured.
    Type: Grant
    Filed: April 13, 2012
    Date of Patent: June 30, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Jian-Bin Shiu, Tung-Sheng Lee
  • Publication number: 20150155321
    Abstract: A semiconductor sensor device is disclosed. The semiconductor sensor device includes a plurality of pixels and a phase grating structure. The phase grating structure has periodically arranged patterns and is disposed on the pixels.
    Type: Application
    Filed: December 2, 2013
    Publication date: June 4, 2015
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Jian-Bin Shiu, Wen-Zheng Yu
  • Publication number: 20150076665
    Abstract: A conductive structure includes a wafer having a scribe line defined thereon, at least a first wiring layer formed in the scribe line, and at least a via layer disposed in the scribe line and under the wiring layer. The first wiring layer includes a main pattern and the via layer includes a closed frame pattern corresponding to the main pattern of the first wiring layer.
    Type: Application
    Filed: September 18, 2013
    Publication date: March 19, 2015
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Jian-Bin Shiu, Min-Ching Chen
  • Patent number: 8885253
    Abstract: A phase grating includes a substrate and a first dielectric layer. The first dielectric layer is disposed on the substrate and includes a column and a plurality of rings. The top sides of the column and the top sides of the rings align with one another to form a flat plane. The column and the rings are concentric.
    Type: Grant
    Filed: June 10, 2014
    Date of Patent: November 11, 2014
    Assignee: United Microelectronics Corp.
    Inventor: Jian-Bin Shiu
  • Publication number: 20140285894
    Abstract: A phase grating includes a substrate and a first dielectric layer. The first dielectric layer is disposed on the substrate and includes a column and a plurality of rings. The top sides of the column and the top sides of the rings align with one another to form a flat plane. The column and the rings are concentric.
    Type: Application
    Filed: June 10, 2014
    Publication date: September 25, 2014
    Inventor: Jian-Bin Shiu
  • Patent number: 8792171
    Abstract: A phase grating includes a substrate and a first dielectric layer. The first dielectric layer is disposed on the substrate and includes a column and a plurality of rings. The top sides of the column and the top sides of the rings align with one another to form a flat plane. The column and the rings are concentric.
    Type: Grant
    Filed: December 5, 2011
    Date of Patent: July 29, 2014
    Assignee: United Microelectronics Corp.
    Inventor: Jian-Bin Shiu
  • Publication number: 20130270557
    Abstract: A monitoring method of a semiconductor process includes the following steps. A semiconductor substrate is provided, and a test structure is formed thereon. The method of forming the test structure includes the following steps. A first doped region and a second doped region are formed in the semiconductor substrate, and an insulating layer is formed on the semiconductor substrate. Subsequently, a conductive layer is directly formed on the insulating layer to complete the formation of the test structure, in which the conductive layer in a floating state partially overlaps the first doped region and partially overlaps the second doped region. Then, a voltage signal is applied to the test structure and the breakdown voltage (Vbd) between the first doped region and the second doped region is measured.
    Type: Application
    Filed: April 13, 2012
    Publication date: October 17, 2013
    Inventors: Jian-Bin Shiu, Tung-Sheng Lee
  • Patent number: 8193605
    Abstract: A bipolar junction transistor (BJT) integrated with a PIP capacitor includes a substrate including a bipolar junction transistor region and a PIP capacitor region, a bipolar junction transistor disposed in the bipolar junction transistor region and extending an isolation layer to the PIP capacitor region and a base poly layer disposed on the isolation layer, and a PIP capacitor disposed in the PIP capacitor region and including a lower poly layer, the isolation layer and the base poly layer to selectively form a PIP capacitor.
    Type: Grant
    Filed: May 7, 2009
    Date of Patent: June 5, 2012
    Assignee: United Microelectronics Corp.
    Inventor: Jian-Bin Shiu
  • Publication number: 20120075702
    Abstract: A phase grating includes a substrate and a first dielectric layer. The first dielectric layer is disposed on the substrate and includes a column and a plurality of rings. The top sides of the column and the top sides of the rings align with one another to form a flat plane. The column and the rings are concentric.
    Type: Application
    Filed: December 5, 2011
    Publication date: March 29, 2012
    Inventor: Jian-Bin Shiu
  • Patent number: 8092699
    Abstract: A method for forming a phase grating is disclosed. First, a substrate is provided. Second, a first dielectric layer with a tapered recess or bulge is formed on the substrate. Later, a second dielectric layer is formed to fill the tapered recess and to cover the first dielectric layer. Afterwards, the second dielectric layer is selectively etched to form the phase grating. The phase grating includes a column and multiple rings. The column and multiple rings are concentric and the multiple rings are disposed on the tapered side so that the height of each ring is different.
    Type: Grant
    Filed: October 21, 2008
    Date of Patent: January 10, 2012
    Assignee: United Microelectronics Corp.
    Inventor: Jian-Bin Shiu
  • Patent number: 7943529
    Abstract: A passivation structure and fabricating method thereof includes providing a chip having a main die region and a scribe line region defined thereon and a plurality of metal pads respectively positioned in the main die region and the scribe line region, forming a first patterned passivation layer having a plurality of first openings and second openings respectively exposing the metal pads in the main die region and the scribe line region on the chip, and forming a second patterned passivation layer filling the first openings in the scribe line region and having a plurality of third openings corresponding to the first openings thus exposing the metal pads in the main die region.
    Type: Grant
    Filed: December 22, 2008
    Date of Patent: May 17, 2011
    Assignee: United Microelectronics Corp.
    Inventor: Jian-Bin Shiu
  • Publication number: 20100283123
    Abstract: A bipolar junction transistor (BJT) integrated with a PIP capacitor includes a substrate including a bipolarjunction transistor region and a PIP capacitor region, a bipolar junction transistor disposed in the bipolar junction transistor region and extending an isolation layer to the PIP capacitor region and a base poly layer disposed on the isolation layer, and a PIP capacitor disposed in the PIP capacitor region and including a lower poly layer, the isolation layer and the base poly layer to selectively form a PIP capacitor.
    Type: Application
    Filed: May 7, 2009
    Publication date: November 11, 2010
    Inventor: Jian-Bin Shiu
  • Publication number: 20100155908
    Abstract: A passivation structure and fabricating method thereof includes providing a chip having a main die region and a scribe line region defined thereon and a plurality of metal pads respectively positioned in the main die region and the scribe line region, forming a first patterned passivation layer having a plurality of first openings and second openings respectively exposing the metal pads in the main die region and the scribe line region on the chip, and forming a second patterned passivation layer filling the first openings in the scribe line region and having a plurality of third openings corresponding to the first openings thus exposing the metal pads in the main die region.
    Type: Application
    Filed: December 22, 2008
    Publication date: June 24, 2010
    Inventor: Jian-Bin Shiu
  • Publication number: 20100096359
    Abstract: A method for forming a phase grating is disclosed. First, a substrate is provided. Second, a first dielectric layer with a tapered recess or bulge is formed on the substrate. Later, a second dielectric layer is formed to fill the tapered recess and to cover the first dielectric layer. Afterwards, the second dielectric layer is selectively etched to form the phase grating. The phase grating includes a column and multiple rings. The column and multiple rings are concentric and the multiple rings are disposed on the tapered side so that the height of each ring is different.
    Type: Application
    Filed: October 21, 2008
    Publication date: April 22, 2010
    Inventor: Jian-Bin Shiu
  • Patent number: 6570145
    Abstract: A phase grating image-sensing device. The device includes a plurality of photodiodes, a smoothing layer, a color filter layer and a plurality of phase gratings. The photodiodes are formed on a substrate and isolated from each other by isolation structures. The smoothing layer covers the photodiodes and the isolation structures. The color filter layer is embedded within the smoothing layer forming a sandwich structure with the smoothing layer. The phase gratings are formed over the smoothing layer positioned at corresponding locations above isolation structures. The phase grating layers produce a constructive interference of light passing through the smoothing layer.
    Type: Grant
    Filed: May 2, 2001
    Date of Patent: May 27, 2003
    Assignee: United Microelectronics Corp.
    Inventors: Chin-Wen Huang, Jian-Bin Shiu, Ching-Ming Lee