Abstract: A circuit and a method for performing a memory built in self test (MBIST) are provided. The circuit comprises a plurality of routing boxes and a test controller. The test controller provides test input signals to a plurality of embedded memory blocks, receives data output signals output by the memory blocks in response to the test input signals, and verifies the data output signal based on the test input signals. The routing boxes are placed to form a common bus between the test controller and the memory blocks to transmit the signals between the test controller and the memory blocks.

Abstract: A circuit and a method for performing a memory built in self test (MBIST) are provided. The circuit comprises a plurality of routing boxes and a test controller. The test controller provides test input signals to a plurality of embedded memory blocks, receives data output signals output by the memory blocks in response to the test input signals, and verifies the data output signal based on the test input signals. The routing boxes are placed to form a common bus between the test controller and the memory blocks to transmit the signals between the test controller and the memory blocks.

Abstract: A digital controlled oscillator (DCO) of a digital phase lock loop (PLL) is disclosed, wherein a fractional DCO structure is employed to provide the required target clock for comparing with the generated output clock. Comparison results of phase differences then enable a K-counter loop filter for changing its stored value. A control logic circuit is enabled to control a tapped-delay line for adjusting the currently output 'clock to coincide the requirement of the target clock when the stored value increases/decreases to K/−K. Additionally, signals from all-digital counter filter can be input to the fractional DCO structure to calibrate the frequency of the target clock according to environment without additional circuits.