Patents by Inventor Jian-Feng Chen
Jian-Feng Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240387277Abstract: A method includes forming a first gate dielectric, a second gate dielectric, and a third gate dielectric over a first semiconductor region, a second semiconductor region, and a third semiconductor region, respectively. The method further includes depositing a first lanthanum-containing layer overlapping the first gate dielectric, and depositing a second lanthanum-containing layer overlapping the second gate dielectric. The second lanthanum-containing layer is thinner than the first lanthanum-containing layer. An anneal process is then performed to drive lanthanum in the first lanthanum-containing layer and the second lanthanum-containing layer into the first gate dielectric and the second gate dielectric, respectively. During the anneal process, the third gate dielectric is free from lanthanum-containing layers thereon.Type: ApplicationFiled: July 25, 2024Publication date: November 21, 2024Inventors: Wen-Hung Huang, Kuo-Feng Yu, Jian-Hao Chen, Shan-Mei Liao, Jer-Fu Wang, Yung-Hsiang Chan
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Publication number: 20240387639Abstract: A semiconductor structure includes a stack of nanostructures, an interfacial layer wrapping around each nanostructure of the stack of nanostructures, a first gate dielectric layer wrapping around the interfacial layer and each nanostructure of the stack of nanostructures, and a gate electrode layer disposed over the first gate dielectric layer. The first gate dielectric layer includes a dipole element. A first concentration of the dipole element at a center line of the first gate dielectric layer is greater than a second concentration of the dipole element at a boundary surface of the first gate dielectric layer interfacing the interfacial layer.Type: ApplicationFiled: July 26, 2024Publication date: November 21, 2024Inventors: Shan-Mei Liao, Yung-Hsiang Chan, Yao-Teng Chuang, Jian-Hao Chen, Kuo-Feng Yu
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Publication number: 20240387682Abstract: A method of forming a semiconductor device includes removing a dummy gate structure to expose a channel region, depositing an interface layer on the channel region, depositing a gate dielectric layer on the interface layer, and forming a doping layer on the gate dielectric layer. The doping layer includes a dipole-inducing element. The method also includes annealing the doping layer to drive the dipole-inducing element through the gate dielectric layer, removing the doping layer, forming a work function metal layer on the gate dielectric layer, depositing an oxygen blocking layer on the work function metal layer, and forming a gate metal fill layer on the oxygen blocking layer.Type: ApplicationFiled: July 25, 2024Publication date: November 21, 2024Inventors: An-Hung Tai, Yung-Hsiang Chan, Shan-Mei Liao, Hsin-Han Tsai, Jian-Hao Chen, Kuo-Feng Yu
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Publication number: 20240381608Abstract: A transistor includes a gate structure that has a first gate dielectric layer and a second gate dielectric layer. The first gate dielectric layer is disposed over the substrate. The first gate dielectric layer contains a first type of dielectric material that has a first dielectric constant. The second gate dielectric layer is disposed over the first gate dielectric layer. The second gate dielectric layer contains a second type of dielectric material that has a second dielectric constant. The second dielectric constant is greater than the first dielectric constant. The first dielectric constant and the second dielectric constant are each greater than a dielectric constant of silicon oxide.Type: ApplicationFiled: July 23, 2024Publication date: November 14, 2024Inventors: Chih-Yu Hsu, Jian-Hao Chen, Chia-Wei Chen, Shan-Mei Liao, Hui-Chi Chen, Yu-Chia Liang, Shih-Hao Lin, Kuei-Lun Lin, Kuo-Feng Yu, Feng-Cheng Yang, Yen-Ming Chen
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Publication number: 20240378817Abstract: According to one embodiment, a method, computer system, and computer program product for head-driven, self-captured photography is provided. The embodiment may include detecting a trigger event performed by a user while the user is interacting with a virtual environment. The embodiment may also include displaying a virtual camera within the virtual environment. The embodiment may further include modifying a location, a distance, and an orientation of the virtual camera in relation to the user based on a plurality of facial movement trigger events by the user. The embodiment may also include capturing one or more images using the virtual camera at the location, the distance, and the orientation based on a facial movement trigger event within the plurality of facial movement trigger events.Type: ApplicationFiled: May 9, 2023Publication date: November 14, 2024Inventors: Xiao Feng Ji, Ya Qing Chen, Chuan Le Zheng, Liang Ying Xu, RUN HUA CHI, Jian Wang
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Publication number: 20240379364Abstract: In an embodiment, a structure includes: a semiconductor substrate; a gate spacer over the semiconductor substrate, the gate spacer having an upper portion and a lower portion, a first width of the upper portion decreasing continually in a first direction extending away from a top surface of the semiconductor substrate, a second width of the lower portion being constant along the first direction; a gate stack extending along a first sidewall of the gate spacer and the top surface of the semiconductor substrate; and an epitaxial source/drain region adjacent a second sidewall of the gate spacer.Type: ApplicationFiled: July 22, 2024Publication date: November 14, 2024Inventors: Yu-Jiun Peng, Hsiu-Hao Tsao, Shu-Han Chen, Chang-Jhih Syu, Kuo-Feng Yu, Jian-Hao Chen, Chih-Hao Yu, Chang-Yun Chang
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Publication number: 20240379796Abstract: A semiconductor device includes a plurality of active region structures that each protrude upwards in a vertical direction. The active region structures each extend in a first horizontal direction. The active region structures are separated from one another in a second horizontal direction different from the first horizontal direction. A gate structure is disposed over the active region structures. The gate structure extends in the second horizontal direction. The gate structure partially wraps around each of the active region structures. A conductive capping layer is disposed over the gate structure. A gate via is disposed over the conductive capping layer. A dimension of the conductive capping layer measured in the second horizontal direction is substantially greater than a maximum dimension of the gate via measured in the second horizontal direction.Type: ApplicationFiled: July 23, 2024Publication date: November 14, 2024Inventors: Chia-Wei Chen, Wei Cheng Hsu, Hui-Chi Chen, Jian-Hao Chen, Kuo-Feng Yu, Shih-Hang Chiu, Wei-Cheng Wang, Kuan-Ting Liu, Yen-Ju Chen, Chun-Chih Cheng, Wei-Chen Hsiao
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Publication number: 20240379365Abstract: A method includes forming a first gate dielectric and a second gate dielectric over a first semiconductor region and a second semiconductor region, respectively, depositing a lanthanum-containing layer including a first portion and a second portion overlapping the first gate dielectric and the second gate dielectric, respectively, and depositing a hard mask including a first portion and a second portion overlapping the first portion and the second portion of the lanthanum-containing layer, respectively. The hard mask is free from both of titanium and tantalum. The method further includes forming a patterned etching mask to cover the first portion of the hard mask, with the second portion of the hard mask being exposed, removing the second portion of the hard mask and the second portion of the lanthanum-containing layer, and performing an anneal to drive lanthanum in the first portion of the lanthanum-containing layer into the first gate dielectric.Type: ApplicationFiled: July 22, 2024Publication date: November 14, 2024Inventors: Kuo-Feng Yu, Chun Hsiung Tsai, Jian-Hao Chen, Hoong Shing Wong, Chih-Yu Hsu
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Patent number: 12142640Abstract: A method includes receiving a workpiece having a first stack of semiconductor layers in a first region and a second stack of semiconductor layers in a second region; forming a first gate dielectric layer surrounding each layer of the first stack and a second gate dielectric layer surrounding each layer of the second stack; forming a first dipole layer surrounding the first gate dielectric layer and merging between vertically adjacent portions of the first gate dielectric layer, and a second dipole layer surrounding the second gate dielectric layer and merging between vertically adjacent portions of the second gate dielectric layer; removing the first dipole layer; after the removing of the first dipole layer, conducting a first annealing on the workpiece; removing a remaining portion of the second dipole layer; and forming a gate electrode layer in the first region and the second region.Type: GrantFiled: September 22, 2021Date of Patent: November 12, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shan-Mei Liao, Yung-Hsiang Chan, Yao-Teng Chuang, Jian-Hao Chen, Kuo-Feng Yu
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Publication number: 20240371970Abstract: A method and structure for doping source and drain (S/D) regions of a PMOS and/or NMOS FinFET device are provided. In some embodiments, a method includes providing a substrate including a fin extending therefrom. In some examples, the fin includes a channel region, source/drain regions disposed adjacent to and on either side of the channel region, a gate structure disposed over the channel region, and a main spacer disposed on sidewalls of the gate structure. In some embodiments, contact openings are formed to provide access to the source/drain regions, where the forming the contact openings may etch a portion of the main spacer. After forming the contact openings, a spacer deposition and etch process may be performed. In some cases, after performing the spacer deposition and etch process, a silicide layer is formed over, and in contact with, the source/drain regions.Type: ApplicationFiled: July 14, 2024Publication date: November 7, 2024Inventors: Chun Hsiung TSAI, Cheng-Yi PENG, Yin-Pin WANG, Kuo-Feng YU, Da-Wen LIN, Jian-Hao CHEN, Shahaji B. MORE
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Publication number: 20240356526Abstract: The disclosed technology generally relates to quartz crystal devices and more particularly to quartz crystal devices configured to vibrate in torsional mode. The quartz crystal device includes a fork-shaped quartz crystal comprising a pair of elongate tines laterally extending from a base region in a horizontal lengthwise direction of the fork-shaped quartz crystal. Each of the tines comprises a line structure vertically protruding out of a central portion of each of top and bottom surfaces thereof and elongated in the horizontal lengthwise direction. The line structures comprise sidewalls, and at least some of the sidewalls and adjoining ones of the top and bottom surfaces of the tines are adjoined by faceted corners. The quartz crystal device also includes first and second electrodes formed on each of the tines, where the first and second electrodes are formed on opposing ones of the sidewalls of each of the line structures.Type: ApplicationFiled: June 25, 2024Publication date: October 24, 2024Inventors: Yue Fang, Jian Feng Chen
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Publication number: 20240332382Abstract: A semiconductor structure includes a substrate, a first transistor disposed over the substrate and including a first channel, a first interfacial layer over the first channel, a first gate dielectric layer over the first interfacial layer, and a first gate electrode layer over the first gate dielectric layer, and a second transistor disposed over the substrate and including a second channel, a second interfacial layer over the second channel, a second gate dielectric layer over the second interfacial layer, and a second gate electrode layer over the second gate dielectric layer. The first gate dielectric layer includes a first dipole material composition having a first maximum concentration at a half-thickness line of the first gate dielectric layer. The second gate dielectric layer includes a second dipole material composition having a second maximum concentration at a half-thickness line of the second gate dielectric layer and greater than the first maximum concentration.Type: ApplicationFiled: June 10, 2024Publication date: October 3, 2024Inventors: Yung-Hsiang Chan, Shan-Mei Liao, Wen-Hung Huang, Jian-Hao Chen, Kuo-Feng Yu, Mei-Yun Wang
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Patent number: 12094948Abstract: A semiconductor device includes a plurality of active region structures that each protrude upwards in a vertical direction. The active region structures each extend in a first horizontal direction. The active region structures are separated from one another in a second horizontal direction different from the first horizontal direction. A gate structure is disposed over the active region structures. The gate structure extends in the second horizontal direction. The gate structure partially wraps around each of the active region structures. A conductive capping layer is disposed over the gate structure. A gate via is disposed over the conductive capping layer. A dimension of the conductive capping layer measured in the second horizontal direction is substantially greater than a maximum dimension of the gate via measured in the second horizontal direction.Type: GrantFiled: September 3, 2021Date of Patent: September 17, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chia-Wei Chen, Wei Cheng Hsu, Hui-Chi Chen, Jian-Hao Chen, Kuo-Feng Yu, Shih-Hang Chiu, Wei-Cheng Wang, Kuan-Ting Liu, Yen-Ju Chen, Chun-Chih Cheng, Wei-Chen Hsiao
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Patent number: 12074206Abstract: A device includes a semiconductor substrate, a fin structure on the semiconductor substrate, a gate structure on the fin structure, and a pair of source/drain features on both sides of the gate structure. The gate structure includes an interfacial layer on the fin structure, a gate dielectric layer on the interfacial layer, and a gate electrode layer of a conductive material on and directly contacting the gate dielectric layer. The gate dielectric layer includes nitrogen element.Type: GrantFiled: August 30, 2021Date of Patent: August 27, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chia-Wei Chen, Chih-Yu Hsu, Hui-Chi Chen, Shan-Mei Liao, Jian-Hao Chen, Cheng-Hao Hou, Huang-Chin Chen, Cheng Hong Yang, Shih-Hao Lin, Tsung-Da Lin, Da-Yuan Lee, Kuo-Feng Yu, Feng-Cheng Yang, Chi On Chui, Yen-Ming Chen
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Patent number: 12074585Abstract: The disclosed technology generally relates to quartz crystal devices and more particularly to quartz crystal devices configured to vibrate in torsional mode. In one aspect, a quartz crystal device configured for temperature sensing comprises a fork-shaped quartz crystal comprising a pair of elongate tines laterally extending from a base region in a horizontal lengthwise direction of the fork-shaped quartz crystal, wherein each of the tines has formed on one or both of opposing sides thereof a pair of vertically recessed groove structures laterally elongated in the horizontal lengthwise direction, wherein the pair of groove structures are separated in a horizontal widthwise direction by a line structure.Type: GrantFiled: May 17, 2023Date of Patent: August 27, 2024Assignee: Statek CorporationInventors: Yue Fang, Jian Feng Chen
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Patent number: 12068371Abstract: A semiconductor device includes a substrate; an isolation structure over the substrate; a fin over the substrate and the isolation structure; a gate structure engaging a first portion of the fin; first sidewall spacers over sidewalls of the gate structure and over a second portion of the fin; source/drain (S/D) features adjacent to the first sidewall spacers; and second sidewall spacers over the isolation structure and over sidewalls of a portion of the S/D features. The second sidewall spacers include silicon oxide, silicon nitride, or silicon oxynitride. The second sidewall spacers and the second portion of the fin include a same dopant, wherein the dopant includes phosphorus.Type: GrantFiled: April 26, 2021Date of Patent: August 20, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chun Hsiung Tsai, Ya-Yun Cheng, Shahaji B. More, Cheng-Yi Peng, Wei-Yang Lee, Kuo-Feng Yu, Yen-Ming Chen, Jian-Hao Chen
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Patent number: 12068392Abstract: A method and structure for doping source and drain (S/D) regions of a PMOS and/or NMOS FinFET device are provided. In some embodiments, a method includes providing a substrate including a fin extending therefrom. In some examples, the fin includes a channel region, source/drain regions disposed adjacent to and on either side of the channel region, a gate structure disposed over the channel region, and a main spacer disposed on sidewalls of the gate structure. In some embodiments, contact openings are formed to provide access to the source/drain regions, where the forming the contact openings may etch a portion of the main spacer. After forming the contact openings, a spacer deposition and etch process may be performed. In some cases, after performing the spacer deposition and etch process, a silicide layer is formed over, and in contact with, the source/drain regions.Type: GrantFiled: March 14, 2022Date of Patent: August 20, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chun Hsiung Tsai, Cheng-Yi Peng, Yin-Pin Wang, Kuo-Feng Yu, Da-Wen Lin, Jian-Hao Chen, Shahaji B. More
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Patent number: 12057486Abstract: The present disclosure provides a semiconductor device and a method of forming the same. The semiconductor device includes a first channel members being vertically stacked, a second channel members being vertically stacked, an n-type work function layer wrapping around each of the first channel members, a first p-type work function layer over the n-type work function layer and wrapping around each of the first channel members, a second p-type work function layer wrapping around each of the second channel members, a third p-type work function layer over the second p-type work function layer and wrapping around each of the second channel members, and a gate cap layer over a top surface of the first p-type work function layer and a top surface of the third p-type work function layer such that the gate cap layer electrically couples the first p-type work function layer and the third p-type work function layer.Type: GrantFiled: March 13, 2023Date of Patent: August 6, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chia-Wei Chen, Wei Cheng Hsu, Hui-Chi Chen, Jian-Hao Chen, Kuo-Feng Yu, Shih-Hang Chiu, Wei-Cheng Wang, Yen-Ju Chen
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Patent number: 12047055Abstract: The disclosed technology generally relates to quartz crystal devices and more particularly to quartz crystal devices configured to vibrate in torsional mode. In one aspect, a quartz crystal device configured for temperature sensing comprises a fork-shaped quartz crystal comprising a pair of elongate tines laterally extending from a base region in a horizontal lengthwise direction of the fork-shaped quartz crystal. Each of the tines has formed on one or both of opposing sides thereof a vertically protruding line structure laterally elongated in the horizontal lengthwise direction. The quartz crystal device further comprises a first electrode and a second electrode formed on the one or both of the opposing sides of each of the tines and configured such that, when an electrical bias is applied between the first and second electrodes, the fork-shaped quartz crystal vibrates in a torsional mode in which each of the tines twists about a respective axis extending in the horizontal lengthwise direction.Type: GrantFiled: May 1, 2023Date of Patent: July 23, 2024Assignee: Statek CorporationInventors: Yue Fang, Jian Feng Chen
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Publication number: 20240243016Abstract: A semiconductor device includes a first transistor located in a first region of a substrate and a second transistor located in a second region of the substrate. The first transistor includes first channel members vertically stacked above the substrate and a first gate structure wrapping around each of the first channel members. The first gate structure includes a first interfacial layer. The second transistor includes second channel members vertically stacked above the substrate and a second gate structure wrapping around each of the second channel members. The second gate structure includes a second interfacial layer. The second interfacial layer has a first sub-layer and a second sub-layer over the first sub-layer. The first and second sub-layers include different material compositions. A total thickness of the first and second sub-layers is larger than a thickness of the first interfacial layer.Type: ApplicationFiled: February 5, 2024Publication date: July 18, 2024Inventors: Chih-Wei Lee, Wen-Hung Huang, Kuo-Feng Yu, Jian-Hao Chen, Hsueh-Ju Chen, Zoe Chen