Abstract: The invention provides a power supply including at least one power output port, at least one status alert component, and at least one output port status monitoring module. The status alert component generates at least one visual prompt based on an alert signal. The output port status monitoring module includes at least one temperature sensor adjacent to the power output port, a microcontroller connected to the temperature sensor and sensing an output current from the power output port, and a reset signal generator connected to the microcontroller. The microcontroller comprises at least one port status alert condition that takes a temperature and the output current of the power output port as decision factors. The microcontroller outputs the alert signal to the status alert component when the port status alert condition is met and maintains the status until a reset signal provided by the reset signal generator is received.

Abstract: The present invention provides a method for managing a flash memory module, wherein the method comprises the steps of: grouping a plurality of blocks within the flash memory module into a plurality of groups, wherein each group comprises at least two blocks; establishing a valid page table, wherein the valid page table records indexes of the plurality of blocks and corresponding numbers of valid pages, respectively; establishing a group minimum valid page array based on the valid page table; referring to the group minimum valid page array to select a target group having a global minimum valid page, wherein the global minimum valid pages is obtained by selecting a minimum value among the minimum valid pages of the groups; searching the at least two blocks within the target group to determine a target block having the global minimum valid pages; and adding the target block into a garbage collection queue.

Abstract: A processor adapted for neural network operation is provided to include a scratchpad memory, a processor core, a neural network accelerator coupled to the processor core, and a arbitration unit coupled to the scratchpad memory, the processor core and the neural network accelerator. The processor core and the neural network accelerator share the scratchpad memory via the arbitration unit.

Abstract: A memory system includes a memory device, a channel and a memory controller device. The memory device includes: a memory array having a read latency, and a write latency that is longer than the read latency; a buffer for two-way data transfer with the memory array; and a transceiver for two-way data transfer with the buffer. The memory controller device is for two-way data transfer with the transceiver through the channel. The memory controller device transmits write data at a write bandwidth for receipt by the transceiver. The transceiver transmits read data at a read bandwidth that is greater than the write bandwidth for receipt by the memory controller device.