Abstract: A method and system for amplifying small optical currents in an optical receiver front end system may employ multiple transimpendance amplifiers (TIAs) and feedback control loops. For example, the front end system may include a main feedback control loop (having a main TIA) and a replica feedback control loop (having a replica TIA) that, collectively, generate an optimum input common mode level for a differential amplifier operating at high data rates (e.g., speeds up to tens of gigabits per second). The replica TIA may track the noise from the power supply of the optical receiver in the substantially same manner as the main TIA. Therefore, the differential signals produced by the main control loop may not be degraded at the input to the high-speed differential amplifier. The outputs of the high-speed differential amplifier may be symmetric about the common mode level and may be suitable inputs for voltage sampling.

Abstract: A method and system for amplifying small optical currents in an optical receiver front end system may employ multiple transimpendance amplifiers (TIAs) and feedback control loops. For example, the front end system may include a main feedback control loop (having a main TIA) and a replica feedback control loop (having a replica TIA) that, collectively, generate an optimum input common mode level for a differential amplifier operating at high data rates (e.g., speeds up to tens of gigabits per second). The replica TIA may track the noise from the power supply of the optical receiver in the substantially same manner as the main TIA. Therefore, the differential signals produced by the main control loop may not be degraded at the input to the high-speed differential amplifier. The outputs of the high-speed differential amplifier may be symmetric about the common mode level and may be suitable inputs for voltage sampling.

Abstract: A circuit configured to sample a signal of a source circuit and to provide calibration signals to a testing device of the signal sampled from the source circuit. The circuit may include an amplifier, a sampling circuit, and a calibration circuit. The amplifier may be configured to drive signals on an internal node to the testing device. The sampling circuit may be configured to provide a sample of a signal from the source circuit to the internal node. The calibration circuit may be configured to provide a first calibration signal and a second calibration signal to the internal node. The second calibration signal may be a known proportion of the first calibration signal.

Abstract: A circuit may include a phase detector circuit, a charge pump circuit, a delay circuit, and a multiplexer circuit. The phase detector circuit may be configured to output a comparison signal based on a comparison of a phase of an inversion of a first clock signal and a phase of a multiplexer signal. The charge pump may be configured to integrate the comparison signal and to output a control voltage based on the integration of the comparison signal. The delay circuit may be configured to receive a second clock signal, to delay the second clock signal based on the control voltage, and to output the delayed second clock signal. The second clock signal may be a divided version of the first clock signal. The multiplexer circuit may be configured to output the multiplexer signal based on the delayed second clock signal.

Abstract: A circuit may include a phase detector circuit, a charge pump circuit, a delay circuit, and a multiplexer circuit. The phase detector circuit may be configured to output a comparison signal based on a comparison of a phase of an inversion of a first clock signal and a phase of a multiplexer signal. The charge pump may be configured to integrate the comparison signal and to output a control voltage based on the integration of the comparison signal. The delay circuit may be configured to receive a second clock signal, to delay the second clock signal based on the control voltage, and to output the delayed second clock signal. The second clock signal may be a divided version of the first clock signal. The multiplexer circuit may be configured to output the multiplexer signal based on the delayed second clock signal.

Abstract: According to at least one embodiment described herein an amplifier may include an amplifying circuit having an output. The amplifier may also include a bandwidth extension circuit coupled to the output of the amplifying circuit. The bandwidth extension circuit may include an active device and a resistor. The active device and the resistor may be configured to create an inductance that increases a bandwidth of the amplifier.

Abstract: A receiver circuit is provided. The receiver circuit may include an amplifying circuit. The amplifying circuit may include an input node, an output node, and a feedback loop coupled between the input node and the output node. The feedback loop may include a first inductor. The amplifying circuit may be configured to receive a current signal on the input node and to output a voltage signal based on the current signal on the output node. The receiver circuit may also include a second inductor with a first node coupled to the input node of the amplifying circuit.

Abstract: In an embodiment, a circuit may include an input node, an output node, an internal node, a compensation circuit, and an adjustable capacitance circuit. The compensation circuit may be configured to modify a return loss of a signal received at the input node. The compensation circuit may include a first inductive element, a second inductive element, and a capacitive element. The first inductive element may couple the input node and the output node. The second inductive element may couple the output node and the internal node. The capacitive element may couple the input node and the internal node. The adjustable capacitance circuit may be configured to adjustably modify the return loss of the signal received at the input node. The capacitance circuit may be coupled to the compensation circuit.

Abstract: A circuit configured to sample a signal of a source circuit and to provide calibration signals to a testing device of the signal sampled from the source circuit. The circuit may include an amplifier, a sampling circuit, and a calibration circuit. The amplifier may be configured to drive signals on an internal node to the testing device. The sampling circuit may be configured to provide a sample of a signal from the source circuit to the internal node. The calibration circuit may be configured to provide a first calibration signal and a second calibration signal to the internal node. The second calibration signal may be a known proportion of the first calibration signal.

Abstract: In an embodiment, a circuit may include an input node, an output node, an internal node, a compensation circuit, and an adjustable capacitance circuit. The compensation circuit may be configured to modify a return loss of a signal received at the input node. The compensation circuit may include a first inductive element, a second inductive element, and a capacitive element. The first inductive element may couple the input node and the output node. The second inductive element may couple the output node and the internal node. The capacitive element may couple the input node and the internal node. The adjustable capacitance circuit may be configured to adjustably modify the return loss of the signal received at the input node. The capacitance circuit may be coupled to the compensation circuit.

Abstract: A low-voltage differential signal driver for high-speed digital transmission includes a first converter operable to receive a signal in a first type and convert the signal into a second type, wherein a resistance of the first converter is variable. A second converter couples to the first converter, the second converter is operable to receive a signal in the second type and convert the signal into the first type, wherein a resistance of the second converter is variable. The driver is operable to scale the resistance of the first and second converters to provide a constant ratio between the resistance of the first and second converters.

Abstract: A low-voltage differential signal driver for high-speed digital transmission includes a first converter operable to receive a signal in a first type and convert the signal into a second type, and a cascode current mirror coupled to the first converter. The cascode current mirror provides an impedance level that increases a differential output voltage.

Abstract: A low-voltage differential signal (LVDS) driver includes at least two programmable fingers operable to drive a signal and at least two pre-drivers. Each pre-driver is associated with one or more of the programmable fingers and is operable to enable or disable the associated one or more programmable fingers. An enabled programmable finger drives the signal and contributes to the capacitive loading of the driver, and a disabled programmable finger does not drive the signal and does not contribute to the capacitive loading of the driver.

Abstract: A low-voltage differential signal driver for high-speed digital transmission includes a first converter operable to receive a signal in a first type and convert the signal into a second type, wherein a resistance of the first converter is variable. A second converter couples to the first converter, the second converter is operable to receive a signal in the second type and convert the signal into the first type, wherein a resistance of the second converter is variable. The driver is operable to scale the resistance of the first and second converters to provide a constant ratio between the resistance of the first and second converters.

Abstract: A low-voltage differential signal driver for high-speed digital transmission includes a first converter operable to receive a signal in a first type and convert the signal into a second type, and a cascode current mirror coupled to the first converter. The cascode current mirror provides an impedance level that increases a differential output voltage.

Abstract: A low-voltage differential signal (LVDS) driver includes at least two programmable fingers operable to drive a signal and at least two pre-drivers. Each pre-driver is associated with one or more of the programmable fingers and is operable to enable or disable the associated one or more programmable fingers. An enabled programmable finger drives the signal and contributes to the capacitive loading of the driver, and a disabled programmable finger does not drive the signal and does not contribute to the capacitive loading of the driver.