Patents by Inventor JIAN-HSIN LU
JIAN-HSIN LU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240401235Abstract: A silicon carbide wafer and a method of fabricating the same are provided. In the silicon carbide wafer, a ratio (V:N) of a vanadium concentration to a nitrogen concentration is in a range of 2:1 to 10:1, and a portion of the silicon carbide wafer having a resistivity greater than 1012 ?·cm accounts for more than 85% of an entire wafer area of the silicon carbide wafer.Type: ApplicationFiled: August 12, 2024Publication date: December 5, 2024Applicant: GlobalWafers Co., Ltd.Inventors: Ching-Shan Lin, Chien-Cheng Liou, Jian-Hsin Lu
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Patent number: 11952676Abstract: A silicon carbide crystal includes a seed layer, a bulk layer and a stress buffering structure formed between the seed layer and the bulk layer. The seed layer, the bulk layer and the stress buffering structure are each formed with a dopant that cycles between high and low dopant concentration. The stress buffering structure includes a plurality of stacked buffer layers and a transition layer over the buffer layers. The buffer layer closest to the seed layer has the same variation trend of the dopant concentration as the buffer layer closest to the transition layer, and the dopant concentration of the transition layer is equal to the dopant concentration of the seed layer.Type: GrantFiled: October 16, 2020Date of Patent: April 9, 2024Assignee: GLOBALWAFERS CO., LTD.Inventors: Ching-Shan Lin, Jian-Hsin Lu, Chien-Cheng Liou, Man-Hsuan Lin
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Publication number: 20230002929Abstract: A silicon carbide crystal includes a seed layer, a bulk layer, and a stress buffering structure formed between the seed layer and the bulk layer. The seed layer, the bulk layer, and the stress buffering structure are each formed with a dopant that cycles between high and low dopant concentration. The stress buffering structure includes a plurality of stacked buffer layers and a transition layer over the buffer layers. The buffer layer closest to the seed layer has the same variation trend of the dopant concentration as the buffer layer closest to the transition layer, and the dopant concentration of the transition layer is equal to the dopant concentration of the seed layer.Type: ApplicationFiled: September 14, 2022Publication date: January 5, 2023Inventors: CHING-SHAN LIN, JIAN-HSIN LU, CHIEN-CHENG LIOU, MAN-HSUAN LIN
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Publication number: 20220025549Abstract: A silicon carbide wafer and a method of fabricating the same are provided. In the silicon carbide wafer, a ratio (V:N) of a vanadium concentration to a nitrogen concentration is in a range of 2:1 to 10:1, and a portion of the silicon carbide wafer having a resistivity greater than 1012 ?·cm accounts for more than 85% of an entire wafer area of the silicon carbide wafer.Type: ApplicationFiled: July 27, 2021Publication date: January 27, 2022Applicant: GlobalWafers Co., Ltd.Inventors: Ching-Shan Lin, Chien-Cheng Liou, Jian-Hsin Lu
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Patent number: 11041255Abstract: A silicon carbide crystal and a manufacturing method thereof are provided. The silicon carbide crystal includes an N-type seed layer, a barrier layer, and a semi-insulating ingot, which are sequentially stacked and are made of silicon carbide. The N-type seed layer has a resistivity within a range of 0.01-0.03 ?·cm. The barrier layer includes a plurality of epitaxial layers sequentially formed on the N-type seed layer by an epitaxial process. The C/Si ratios of the epitaxial layers gradually increase in a growth direction away from the N-type seed layer. A nitrogen concentration of the silicon carbide crystal gradually decreases from the N-type seed layer toward the semi-insulating ingot by a diffusion phenomenon, so that the semi-insulating crystal has a resistivity larger than 107 ?·cm.Type: GrantFiled: June 24, 2019Date of Patent: June 22, 2021Assignee: GlobalWafers Co., Ltd.Inventors: Ching-Shan Lin, Jian-Hsin Lu, Chien-Cheng Liou, I-Ching Li
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Publication number: 20210054525Abstract: A silicon carbide crystal includes a seed layer, a bulk layer and a stress buffering structure formed between the seed layer and the bulk layer. The seed layer, the bulk layer and the stress buffering structure are each formed with a dopant that cycles between high and low dopant concentration. The stress buffering structure includes a plurality of stacked buffer layers and a transition layer over the buffer layers. The buffer layer closest to the seed layer has the same variation trend of the dopant concentration as the buffer layer closest to the transition layer, and the dopant concentration of the transition layer is equal to the dopant concentration of the seed layer.Type: ApplicationFiled: October 16, 2020Publication date: February 25, 2021Inventors: CHING-SHAN LIN, JIAN-HSIN LU, CHIEN-CHENG LIOU, MAN-HSUAN LIN
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Patent number: 10851470Abstract: A silicon carbide crystal and a method for manufacturing the same are disclosed. The silicon carbide crystal includes a seed layer, a bulk layer, and a stress buffering structure formed between the seed layer and the bulk layer. The seed layer, the bulk layer, and the stress buffering structure are each formed with a dopant that cycles between high and low concentration. Therefore, the crystal defects can be significantly reduced.Type: GrantFiled: March 30, 2018Date of Patent: December 1, 2020Assignee: GLOBALWAFERS CO., LTD.Inventors: Ching-Shan Lin, Jian-Hsin Lu, Chien-Cheng Liou, Man-Hsuan Lin
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Publication number: 20200190693Abstract: A silicon carbide crystal and a manufacturing method thereof are provided. The silicon carbide crystal includes an N-type seed layer, a barrier layer, and a semi-insulating ingot, which are sequentially stacked and are made of silicon carbide. The N-type seed layer has a resistivity within a range of 0.01-0.03 ?·cm. The barrier layer includes a plurality of epitaxial layers sequentially formed on the N-type seed layer by an epitaxial process. The C/Si ratios of the epitaxial layers gradually increase in a growth direction away from the N-type seed layer. A nitrogen concentration of the silicon carbide crystal gradually decreases from the N-type seed layer toward the semi-insulating ingot by a diffusion phenomenon, so that the semi-insulating crystal has a resistivity larger than 107 ?·cm.Type: ApplicationFiled: June 24, 2019Publication date: June 18, 2020Inventors: CHING-SHAN LIN, JIAN-HSIN LU, CHIEN-CHENG LIOU, I-CHING LI
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Patent number: 10347481Abstract: A method for producing a silicon carbide wafer includes: providing a silicon carbide wafer having an unpolished surface; in which the unpolished surface has a first crystal face and a second crystal face; polishing one face of the first crystal face and the second crystal face of the unpolished surface in a first polishing solution by using a polisher; in which the polisher includes a polishing pad and a plurality of abrasive particles fixed on the polishing pad; and polishing the other face of the first crystal face and the second crystal face of the unpolished surface in a second polishing solution by using the polisher; in which a pH value of the first polishing solution is less than or equal to 7, and a pH value of the second polishing solution is greater than or equal to 7. The present disclosure also provides a silicon carbide wafer.Type: GrantFiled: December 15, 2017Date of Patent: July 9, 2019Assignee: GlobalWafers Co., Ltd.Inventors: Ching-Shan Lin, Jian-Hsin Lu, Chien-Cheng Liou, I-Ching Li
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Publication number: 20190115205Abstract: A method for producing a silicon carbide wafer includes: providing a silicon carbide wafer having an unpolished surface; in which the unpolished surface has a first crystal face and a second crystal face; polishing one face of the first crystal face and the second crystal face of the unpolished surface in a first polishing solution by using a polisher; in which the polisher includes a polishing pad and a plurality of abrasive particles fixed on the polishing pad; and polishing the other face of the first crystal face and the second crystal face of the unpolished surface in a second polishing solution by using the polisher; in which a pH value of the first polishing solution is less than or equal to 7, and a pH value of the second polishing solution is greater than or equal to 7. The present disclosure also provides a silicon carbide wafer.Type: ApplicationFiled: December 15, 2017Publication date: April 18, 2019Inventors: CHING-SHAN LIN, JIAN-HSIN LU, CHIEN-CHENG LIOU, I-CHING LI
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Publication number: 20190106807Abstract: A silicon carbide crystal and a method for manufacturing the same are disclosed. The silicon carbide crystal includes a seed layer, a bulk layer, and a stress buffering structure formed between the seed layer and the bulk layer. The seed layer, the bulk layer, and the stress buffering structure are each formed with a dopant that cycles between high and low concentration. Therefore, the crystal defects can be significantly reduced.Type: ApplicationFiled: March 30, 2018Publication date: April 11, 2019Inventors: CHING-SHAN LIN, JIAN-HSIN LU, CHIEN-CHENG LIOU, MAN-HSUAN LIN
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Publication number: 20190106811Abstract: A silicon carbide crystal and a manufacturing method for same are provided. A silicon carbide crystal seed used for the silicon carbide crystal has a crystal-growing surface with a surface roughness (Ra) less than 2.0 nm, and a thickness of the silicon carbide crystal seed is less than 700 ?m. Therefore, the silicon carbide crystal grown from the silicon carbide crystal seed by sublimation method (which is also a PVT method) may have low basal plane dislocation (BPD) and low micropipe density (MPD).Type: ApplicationFiled: January 8, 2018Publication date: April 11, 2019Applicant: GlobalWafers Co., Ltd.Inventors: Ching-Shan Lin, Jian-Hsin Lu, Chien-Cheng Liou, I-Ching Li