Abstract: Disclosed herein are related to a system and a method of extending a lifetime of a memory cell. In one aspect, a memory controller applies a first pulse having a first amplitude to the memory cell to write input data to the memory cell. In one aspect, the memory controller applies a second pulse having a second amplitude larger than the first amplitude to the memory cell to extend a lifetime of the memory cell. The memory cell may include a resistive memory device or a phase change random access memory device. In one aspect, the memory controller applies the second pulse to the memory cell to repair the memory cell in response to determining that the memory cell has failed. In one aspect, the memory controller periodically applies the second pulse to the memory cell to extend the lifetime of the memory cell before the memory cell fails.

Abstract: A method of photomask reticle design provides for greatly increased tolerance to adjacent exposure field alignment and/or stepper magnification errors, thus eliminating gaps between adjacent exposure fields in the fabrication of semiconductor integrated circuit devices.The resulting insurance of complete exposure of photoresist eliminates the formation of non-exposed unwanted photoresist residues or stringers, which constitute defects in the manufacture of such devices.

Abstract: A method for forming within an integrated circuit a patterned conductor layer from a blanket conductor layer through a plasma etch method, where there is simultaneously avoided plasma induced electrical discharge damage to an integrated circuit structure formed beneath the blanket conductor layer. There is first provided a substrate. There is then formed over the substrate an integrated circuit structure. There is then formed over the substrate and the integrated circuit structure a blanket conductor layer.

Abstract: A plasma etch method for patterning for use within an integrated circuit a blanket conductor layer such that an integrated circuit layer adjoining the blanket conductor layer is not damaged when the blanket conductor layer is patterned to form a patterned conductor layer through the plasma etch method. There is first provided a semiconductor substrate. There is then formed over the semiconductor substrate a blanket conductor layer, where the blanket conductor layer communicates electrically with the semiconductor substrate in a fashion such that an electrical charge is shunted from the blanket conductor layer into the semiconductor substrate when the blanket conductor layer is patterned to form the patterned conductor layer through the plasma etch method. There is then patterned through the plasma etch method the blanket conductor layer to form the patterned conductor layer.

Abstract: The problem of how to prevent trapping charge during high energy ion implantation, as part of a PLDD, NLDD, PS/D, and NS/D manufacturing process, has been solved through use of a protective cap of photoresist which is applied to the gate prior to the high energy ion implantation. Said protective cap is readily removed after ion implantation.