Abstract: A transceiver connector (100) includes a housing (1) having a number of faces including a primary face (10) and a pair of side faces (13) and a collar clip (2). The collar clip includes a base at least partially surrounding the plurality of faces of the housing. The primary face defines at least one vertically extending locking recess (104) having a stepped portion (1041). The collar clip includes a base (20) at least partially surrounding the number of faces of the housing. The base includes at least one locking beam (204) inserted into the corresponding locking recess of the housing along a first direction and having a click portion (2041) engaging with the stepped portion of the housing along a second direction perpendicular to the first direction.

Abstract: An electrical connector assembly (100) including a housing (1) having a channel (12) formed on a top surface thereof and extending along a mating direction, a latch mechanism (6) received in the channel and being capable of sliding in the channel, and a spring (8) received in the indentation. An indentation (1216) is formed in the channel. The spring is limited by the latch mechanism along a front to rear direction. The latch mechanism defines a block (6202) extending into the indentation and attached to a front end of the spring.

Abstract: A connector assembly includes a receptacle (200) having a latching tab (2) defining a latching hole (21) and a plug connector (100). The plug connector includes a housing (1) having a latching nose (111) for latching with the latching hole and a releasing mechanism. The releasing mechanism includes two resisting beams (53) disposed on the housing and having two protrusions (531), a puller (71), and an operator (72) having two guiding portions (722) projecting toward and in front of the protrusions. The guiding portions slide beneath the protrusions, in response to a rearward movement of the puller, to tilt the resisting beams upwardly and lift the latching tab from a latched position to a released position for releasing the latching nose from the latching hole.

Abstract: A transceiver connector (100) includes a housing (1) having a number of faces including a primary face (10) and a pair of side faces (13) and a collar clip (2). The collar clip includes a base at least partially surrounding the plurality of faces of the housing. The primary face defines at least one vertically extending locking recess (104) having a stepped portion (1041). The collar clip includes a base (20) at least partially surrounding the number of faces of the housing. The base includes at least one locking beam (204) inserted into the corresponding locking recess of the housing along a first direction and having a click portion (2041) engaging with the stepped portion of the housing along a second direction perpendicular to the first direction.

Abstract: A connector assembly includes a receptacle (200) having a latching tab (2) defining a latching hole (21) and a plug connector (100). The plug connector includes a housing (1) having a latching nose (111) for latching with the latching hole and a releasing mechanism. The releasing mechanism includes two resisting beams (53) disposed on the housing and having two protrusions (531), a puller (71), and an operator (72) having two guiding portions (722) projecting toward and in front of the protrusions. The guiding portions slide beneath the protrusions, in response to a rearward movement of the puller, to tilt the resisting beams upwardly and lift the latching tab from a latched position to a released position for releasing the latching nose from the latching hole.

Abstract: A cable assembly (100) includes a cover (40) defining a cavity (101), a circuit board (20) assembled in the cavity and including a first surface (201) and a second surface (202) lower than the first surface, and a cable (2) having a jacket (22) and a number of wires (21) shrouded by the jacket. Each wire includes an inner coat (210) and a conductor having a free end (211) exposed outwardly from the inner coat for being soldered to the first surface, with the inner coat disposed on the second surface.

Abstract: An apparatus for adjusting a pixel clock frequency based on a phase locked loop (PLL) includes: a pixel clock generator (11) for generating an actual pixel clock having an actual frequency; a division frequency counter (12) for dividing the actual pixel clock into several pixel clocks having different frequency ranges by means of multiplying the actual frequency of the actual pixel clock by a multiplier; a reference frequency counter (13) for dividing the actual pixel clock by means of lowering the actual frequency of the actual pixel clock, and generating a reference frequency; a reactive frequency counter (14) for dividing the actual pixel clock by means of heightening the actual frequency of the actual pixel clock, and generating a reactive frequency; a PLL circuit (16) for integrating the reference frequency and the reactive frequency to generate a required pixel clock having a required frequency. A related method is also disclosed.

Abstract: A system for checking basic input output system read only memory (BIOS ROM) data includes a keyboard, a display, a computer host, and a checking device. The computer host has a BIOS ROM installed therein. The checking device includes: a data dividing module for dividing the BIOS ROM data into a plurality of sections; a data obtaining module for capturing BIOS ROM data from one or more sections, and for counting a check datum; a data checking module for comparing the check datum with a standard datum, and for determining whether the two data are equal; and a checking result outputting module for outputting the checking results.

Abstract: A video graphics array color signal generator is provided. The signal generator includes an FPGA (field program gate array) device (1), a PROM (programmable read only memory) (2), a PLL (phase locked loop) circuit (3), a D/A (digital/analog) convertor (4) connected with the FPGA device, a VGA (video graphics array) interface (5), a pixel clock generator (6) which generates pixel clocks continuously at a frequency, and a keyboard (7) which provides operating buttons for users.

Abstract: A video graphic array colorful signal generator is provided. The signal generator includes a FPGA (field program gate array) device (1), a PROM (programmable read only memory) (2), a PLL (phase locked loop) circuit (3), a D/A (digital/analog) convertor (4) connected with the FPGA device, a VGA (video graphic array) interface (5), a pixel clock generator (6) which generates pixel clock continuously at a frequency, and a keyboard (7) which provides operating buttons for users.

Abstract: An apparatus for adjusting a pixel clock frequency based on a phase locked loop (PLL) includes: a pixel clock generator (11) for generating an actual pixel clock having an actual frequency; a division frequency counter (12) for dividing the actual pixel clock into several pixel clocks having different frequency ranges by means of multiplying the actual frequency of the actual pixel clock by a multiplier; a reference frequency counter (13) for dividing the actual pixel clock by means of lowering the actual frequency of the actual pixel clock, and generating a reference frequency; a reactive frequency counter (14) for dividing the actual pixel clock by means of heightening the actual frequency of the actual pixel clock, and generating a reactive frequency; a PLL circuit (16) for integrating the reference frequency and the reactive frequency to generate a required pixel clock having a required frequency. A related method is also disclosed.

Abstract: The present invention provides a system for checking drivers of hardware devices of a computer (10). The system includes: a traveling module (101) for traveling a tree structure of the drivers by accessing the System Regedit of the computer through an application programming interface; a retrieving module (102) for retrieving an error code for each of the drivers and contents of an initialization file which includes information on a version of each of the drivers; and a determining module (103) for determining whether a driver is installed properly according to the corresponding error code, and for determining whether the driver has a correct version according to the contents of the initialization file. A related method is also provided.

Abstract: A system for checking BIOS ROM data is disclosed. The system includes a keyboard (10), a display (20), a computer host (30), and a checking device (40). The computer host (30) has a BIOS ROM (301) installed therein. The checking device (40) includes: a data dividing module (400) for dividing the BIOS ROM data into a plurality of sections; a data obtaining module (401) for capturing BIOS ROM data from one or more sections, and for counting a check datum; a data checking module (402) for comparing the check datum with a standard datum, and for determining whether the two data are equal; and a checking result outputting module (403) for outputting the checking results. A related method is also disclosed.