Abstract: A filter structure and a filter device provided by the present application relate to the technical field of electronic devices. The filter structure includes: a shielding component, which includes a first shielding layer and a second shielding layer, which are arranged opposite each other at an interval; at least two resonance components, which are arranged at an interval, wherein each resonance component includes a resonance column and a resonance disk connected to the resonance column, and the resonance column is located between the first shielding layer and the second shielding layer and is connected to the first shielding layer; and a coupling enhancement component, which is respectively arranged at intervals from the first shielding layer and the second shielding layer, and is respectively connected to at least two resonance columns, so as to increase a coupling coefficient between the at least two resonance columns.

Abstract: A query optimization method includes: obtaining a plurality of query tasks to be optimized, each query task including at least one subtask, and when a same query task includes at least two subtasks, a query dependence relationship existing between the at least two subtasks; combining the plurality of query tasks based on the query dependence relationship to obtain a combined task; and merging at least two subtasks in different query tasks of the plurality of query tasks based on the combined task to obtain a first merged subtask, the first merged subtask being executed to obtain query results of the at least two subtasks in the different query tasks.

Abstract: Disclosed are a method and system for improving timing closure in chip design. The method comprises: identifying a critical timing path in a chip design pattern, wherein a timing window of the critical timing path is smaller than a predetermined timing window; determining a variation of each segment of the critical timing path, wherein the variation indicates uncertainty of delay of a device and/or a wire caused by one or more factors; and changing at least one segment of the critical timing path based on the variation of each segment of the critical timing path to enlarge the timing window of the critical timing path. The method and system may enlarge a timing window of a critical timing path by reducing the variation thereof, thereby achieving timing closure in the chip design pattern.

Abstract: Disclosed are a method and system for improving timing closure in chip design. The method comprises: identifying a critical timing path in a chip design pattern, wherein a timing window of the critical timing path is smaller than a predetermined timing window; determining a variation of each segment of the critical timing path, wherein the variation indicates uncertainty of delay of a device and/or a wire caused by one or more factors; and changing at least one segment of the critical timing path based on the variation of each segment of the critical timing path to enlarge the timing window of the critical timing path. The method and system may enlarge a timing window of a critical timing path by reducing the variation thereof, thereby achieving timing closure in the chip design pattern.