Patents by Inventor Jian Qiang Ni

Jian Qiang Ni has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Data structure for flash memory and data reading/writing method thereof
    Patent number: 8327230
    Abstract: A data structure for a flash memory and data reading/writing method thereof are disclosed. A 512 bytes data and a redundant code derived from the data encoded with a 6-bit error correcting code scheme are stored in a first sector and a second sector with sequential address in a block of the flash memory respectively. A logic block address information of this block is divided into two parts that are stored in the first sector and the second sector respectively.
    Type: Grant
    Filed: January 6, 2012
    Date of Patent: December 4, 2012
    Assignee: Realtek Semiconductor Corp.
    Inventors: Jian-Qiang Ni, Dong-Yu He, Chun-Ting Liao
  • Data Structure for Flash Memory and Data Reading/Writing Method Thereof
    Publication number: 20120110419
    Abstract: A data structure for a flash memory and data reading/writing method thereof are disclosed. A 512 bytes data and a redundant code derived from the data encoded with a 6-bit error correcting code scheme are stored in a first sector and a second sector with sequential address in a block of the flash memory respectively. A logic block address information of this block is divided into two parts that are stored in the first sector and the second sector respectively.
    Type: Application
    Filed: January 6, 2012
    Publication date: May 3, 2012
    Applicant: REALTEK SEMICONDUCTOR CORP.
    Inventors: Jian-Qiang Ni, Dong-Yu He, Chun-Ting Liao
  • Data structure for flash memory and data reading/writing method thereof
    Patent number: 8122303
    Abstract: A data structure for a flash memory and data reading/writing method thereof are disclosed. A 512 bytes data and a redundant code derived from the data encoded with a 6-bit error correcting code scheme are stored in a first sector and a second sector with sequential address in a block of the flash memory respectively. A logic block address information of this block is divided into two parts that are stored in the first sector and the second sector respectively.
    Type: Grant
    Filed: May 19, 2008
    Date of Patent: February 21, 2012
    Assignee: Realtek Semiconductor Corp.
    Inventors: Jian-Qiang Ni, Dong-Yu He, Chun-Ting Liao
  • Data writing method for flash memory and error correction encoding/decoding method thereof
    Patent number: 8055983
    Abstract: A data writing method for flash memory and an error correction encoding/decoding method thereof are disclosed. In an embodiment of the data writing method, a 6-bit ECC scheme using a Reed-Solomon code derived from a Galois Field GF (29) is used to encode a data for generating a redundant which requires smaller storing space. In an embodiment of the error correction encoding/decoding method, an erase checking value corresponding to the status where all the bytes of data area and parameter storing area are “0xff” is provided to improve the security of stored data.
    Type: Grant
    Filed: May 23, 2008
    Date of Patent: November 8, 2011
    Assignee: Realtek Semiconductor Corp.
    Inventors: Jian Qiang Ni, Dong Yu He, Chun Ting Liao
  • Data Writing Method For Flash Memory and Error Correction Encoding/Decoding Method Thereof
    Publication number: 20080294965
    Abstract: A data writing method for flash memory and an error correction encoding/decoding method thereof are disclosed. In an embodiment of the data writing method, a 6-bit ECC scheme using a Reed-Solomon code derived from a Galois Field GF (29) is used to encode a data for generating a redundant which requires smaller storing space. In an embodiment of the error correction encoding/decoding method, an erase checking value corresponding to the status where all the bytes of data area and parameter storing area are “0xff” is provided to improve the security of stored data.
    Type: Application
    Filed: May 23, 2008
    Publication date: November 27, 2008
    Applicant: Realtek Semiconductor Corp.
    Inventors: Jian-Qiang Ni, Dong-Yu He, Chun-Ting Liao
  • DATA STRUCTURE FOR FLASH MEMORY AND DATA READING/WRITING METHOD THEREOF
    Publication number: 20080294935
    Abstract: A data structure for a flash memory and data reading/writing method thereof are disclosed. A 512 bytes data and a redundant code derived from the data encoded with a 6-bit error correcting code scheme are stored in a first sector and a second sector with sequential address in a block of the flash memory respectively. A logic block address information of this block is divided into two parts that are stored in the first sector and the second sector respectively.
    Type: Application
    Filed: May 19, 2008
    Publication date: November 27, 2008
    Inventors: Jian-Qiang NI, Dong-Yu He, Chun-Ting Liao