Abstract: A video transmitting circuit and a signal delay compensation method thereof are provided. The video transmitting circuit transmits a specific signal through a first transmission path and a second transmission path to a video receiver during a calibration mode. In the calibration mode, a return detection circuit of the video transmitting circuit detects whether or not a first return signal transmitted through the first transmission path and a second return signal transmitted through the second transmission path have been received by the video transmitting circuit. The video transmitting circuit sets delay circuits serially connected in the first or second transmission path according to a detection result of the return detection circuit, such that the first return signal transmitted through the first transmission path and the second return signal transmitted through the second transmission path can synchronously arrive at the video receiver.

Abstract: A video transmitting circuit and a signal delay compensation method thereof are provided. The video transmitting circuit transmits a specific signal through a first transmission path and a second transmission path to a video receiver during a calibration mode. In the calibration mode, a return detection circuit of the video transmitting circuit detects whether or not a first return signal transmitted through the first transmission path and a second return signal transmitted through the second transmission path have been received by the video transmitting circuit. The video transmitting circuit sets delay circuits serially connected in the first or second transmission path according to a detection result of the return detection circuit, such that the first return signal transmitted through the first transmission path and the second return signal transmitted through the second transmission path can synchronously arrive at the video receiver.

Abstract: A method and a device for finding a square root are provided. The method includes the following steps: storing an unsigned integer into a first register in the form of an N-bit binary code, N being an even number greater than zero; using an operation circuit to determine whether or not the (N?1)th to [N?(2×i)]th bits of the unsigned integer are greater than or equal to the ith integer square root; if yes, outputting 1 as the value of the [(N/2)?i]th bit of the square root of the unsigned integer and storing the same into a second register; and if not, outputting 0 as the value of the [(N/2)?i]th bit of the square root of the unsigned integer and storing the same into the second register, i being an integer ranging from 1 to (N/2).

Abstract: A video encoding circuit electrically connected to a digital to analog converter (DAC) for encoding a first digital image signal to a second digital image signal is provided. The first digital image signal includes a luminance signal, a color signal and a decoding synchronization signal. The video encoding circuit includes a compensation circuit, a color generation circuit and a video composite circuit. The compensation circuit determines a selected level corresponding to the luminance signal. The color generation circuit electrically connected to the compensation circuit generates a color carrier signal according to the selected level and the color signal. The video composite circuit is connected to the color generation circuit, the compensation circuit, and the DAC. The video composite circuit generates the second digital image signal according to the luminance signal, the decoding synchronization signal, and the color carrier signal, and outputs the second digital image signal to the DAC.