Abstract: A semiconductor electrochemical plating (ECP) tool includes: a plating cell which receives an ECP solution therein; a support onto which a semiconductor substrate is selectively secured, the support being controllable to selectively dip the semiconductor substrate into ECP solution contained in the plating cell; a recirculation system including a reservoir that receives an overflow of ECP solution from the plating cell, the ECP solution being recirculated from the reservoir back to the plating cell; a bubble monitoring system that detects gas bubbles within the ECP solution; and a degassing system that inhibits at least one of gas bubble formation, nucleation and growth within the ECP solution, wherein the degassing system is controlled at least in part based upon gas bubble detection by the bubble monitoring system.

Abstract: Some implementations described herein provide techniques and apparatuses for forming a copper structure adjacent to a multi-layer film structure included in a semiconductor device. The techniques include using an electroplating process to form the copper structure adjacent to the multi-layer film structure, wherein a pre-layer of chlorine molecules coats a seed layer of the multi-layer film structure during the electroplating process. During formation of the copper structure, a chlorine-enriched interface region (e.g., a control layer including a copper chelate material with chlorine) may be formed between the copper structure and the multi-layer film structure including the seed layer. The chlorine-enriched interface region may reduce a likelihood of electromigration and/or stress migration within the semiconductor device.

Abstract: A buffer layer may be included between a first conductive electrode layer and an insulator layer, and/or between a second conductive electrode layer and the insulator layer of a capacitor structure to reduce lattice mismatching in the capacitor structure. The buffer layer(s) include a combination of materials that promote lattice matching between the insulator layer and one or more of the conductive electrode layers. This reduces the likelihood of formation of structural defects in the capacitor structure relative to another capacitor structure that does not include the buffer layers.

Abstract: Embodiments of the present disclosure relate to methods of fabricating conductive features to prevent metal extrusion. Particularly, the conductive feature includes a control layer to reduce grain size of a metal containing layer, thus obtaining a robust structure to decrease extrusion defects. In some embodiments, the control layer is formed between a barrier layer and the conductive feature. In some embodiments, the control layer is formed by adding a control element, such as oxygen, to an upper portion of the barrier layer.

Abstract: A plurality of radiation-sensing doped regions are formed in a substrate. A trench is formed in the substrate between the radiation-sensing doped regions. A SiOCN layer is filled in the trench by reacting Bis(tertiary-butylamino)silane (BTBAS) and a gas mixture comprising N2O, N2 and O2 through a plasma enhanced atomic layer deposition (PEALD) method, to form an isolation structure between the radiation-sensing doped regions.

Abstract: A device includes a semiconductor substrate having a front side and a backside. A photo-sensitive device is disposed at a surface of the semiconductor substrate, wherein the photo-sensitive device is configured to receive a light signal from the backside of the semiconductor substrate, and convert the light signal to an electrical signal. An amorphous-like adhesion layer is disposed on the backside of the semiconductor substrate. The amorphous-like adhesion layer includes a compound of nitrogen and a metal. A metal shielding layer is disposed on the backside of the semiconductor substrate and contacting the amorphous-like adhesion layer.

Abstract: A plurality of radiation-sensing doped regions are formed in a substrate. A trench is formed in the substrate between the radiation-sensing doped regions. A SiOCN layer is filled in the trench by reacting Bis(tertiary-butylamino)silane (BTBAS) and a gas mixture comprising N2O, N2 and O2 through a plasma enhanced atomic layer deposition (PEALD) method, to form an isolation structure between the radiation-sensing doped regions.

Abstract: An image sensor includes a substrate having a first region and a second region. The image sensor further includes a dielectric layer over the substrate. The image sensor further includes a conductive layer over the dielectric layer, wherein in the first region the conductive layer has a grid shape and in the second region a portion of the conductive layer is concave toward the substrate. The image sensor further includes a protective layer, wherein the protective layer is over the conductive layer in the first region, and over a top surface and along sidewalls of the conductive layer in the second region.

Abstract: A device includes a semiconductor substrate having a front side and a backside. A photo-sensitive device is disposed at a surface of the semiconductor substrate, wherein the photo-sensitive device is configured to receive a light signal from the backside of the semiconductor substrate, and convert the light signal to an electrical signal. An amorphous-like adhesion layer is disposed on the backside of the semiconductor substrate. The amorphous-like adhesion layer includes a compound of nitrogen and a metal. A metal shielding layer is disposed on the backside of the semiconductor substrate and contacting the amorphous-like adhesion layer.

Abstract: A device includes a semiconductor substrate having a front side and a backside. A photo-sensitive device is disposed at a surface of the semiconductor substrate, wherein the photo-sensitive device is configured to receive a light signal from the backside of the semiconductor substrate, and convert the light signal to an electrical signal. An amorphous-like adhesion layer is disposed on the backside of the semiconductor substrate. The amorphous-like adhesion layer includes a compound of nitrogen and a metal. A metal shielding layer is disposed on the backside of the semiconductor substrate and contacting the amorphous-like adhesion layer.

Abstract: An image sensor includes a substrate having a first region and a second region. The image sensor further includes a dielectric layer over the substrate. The image sensor further includes a conductive layer over the dielectric layer, wherein in the first region the conductive layer has a grid shape and in the second region a portion of the conductive layer is concave toward the substrate. The image sensor further includes a protective layer, wherein the protective layer is over the conductive layer in the first region, and over a top surface and along sidewalls of the conductive layer in the second region.

Abstract: A semiconductor structure includes a first dielectric layer, a first conductive via, a second conductive via and an etch stop layer. The first conductive via and the second conductive via are respectively disposed in the first dielectric layer. The etch stop layer is disposed on the first dielectric layer and contacts the first and second conductive vias. The etch stop layer includes nitrogen-and-oxygen-doped silicon carbide (NODC).

Abstract: A semiconductor structure includes a first dielectric layer, a first conductive via, a second conductive via and an etch stop layer. The first conductive via and the second conductive via are respectively disposed in the first dielectric layer. The etch stop layer is disposed on the first dielectric layer and contacts the first and second conductive vias. The etch stop layer includes nitrogen-and-oxygen-doped silicon carbide (NODC).

Abstract: A method of fabricating an image sensor includes depositing a first dielectric layer over a substrate, removing a portion of the first dielectric layer from the substrate to form a trench, depositing a conductive layer over the first dielectric layer and in the trench, forming a protective layer lining a top surface of the conductive layer and sidewalls and a bottom surface of the groove in the conductive layer, and removing a portion of the conductive layer to form a grid structure. A groove corresponding to the trench is formed in the conductive layer.

Abstract: A method of fabricating an image sensor includes depositing a first dielectric layer over a substrate, removing a portion of the first dielectric layer from the substrate to form a trench, depositing a conductive layer over the first dielectric layer and in the trench, forming a protective layer lining a top surface of the conductive layer and sidewalls and a bottom surface of the groove in the conductive layer, and removing a portion of the conductive layer to form a grid structure. A groove corresponding to the trench is formed in the conductive layer.

Abstract: A semiconductor device includes a substrate, a dielectric structure, a top metal layer and a bonding structure. The dielectric structure is disposed on the substrate. The top metal layer is disposed in the dielectric structure. The bonding structure is disposed on the dielectric structure and the top metal layer. The bonding structure includes a silicon oxide layer, a silicon oxy-nitride layer, a conductive bonding layer and a barrier layer. The silicon oxide layer is disposed on the dielectric structure. The silicon oxy-nitride layer covers the silicon oxide layer. The conductive bonding layer is disposed in the silicon oxide layer and the silicon oxy-nitride layer. The barrier layer covers a sidewall and a bottom of the conductive bonding layer.

Abstract: Semiconductor devices and manufacturing method thereof are disclosed. The semiconductor device includes a substrate, a device layer, first and second conductive layers, first and second vias, and a MIM capacitor structure. The substrate includes active and passive regions. The device layer is in the active region. The first conductive layer is over the device layer. The second conductive layer is over the first conductive layer, wherein the first conductive layer is disposed between the device layer and the second conductive layer. The first via electrically connects the first and the second conductive layers. The MIM capacitor structure is between the first and the second conductive layers and in the passive region, and includes first and second electrodes and a capacitor dielectric layer therebetween. The capacitor dielectric layer includes Group IIIA-metal oxide or nitride. The second via electrically connects the second conductive layer and one of the first and second electrodes.

Abstract: A memory cell includes a selector, a fuse connected to the selector in series, a contact etch stop layer formed on the selector and the fuse, a bit line connected to the fuse, and a word line connected to the selector. The contact etch stop layer includes a high-k dielectric for improving the ability of capturing the electrons, thus the retention time of the memory cell is increased.

Abstract: A semiconductor device includes a substrate, a dielectric structure, a top metal layer and a bonding structure. The dielectric structure is disposed on the substrate. The top metal layer is disposed in the dielectric structure. The bonding structure is disposed on the dielectric structure and the top metal layer. The bonding structure includes a silicon oxide layer, a silicon oxy-nitride layer, a conductive bonding layer and a barrier layer. The silicon oxide layer is disposed on the dielectric structure. The silicon oxy-nitride layer covers the silicon oxide layer. The conductive bonding layer is disposed in the silicon oxide layer and the silicon oxy-nitride layer. The barrier layer covers a sidewall and a bottom of the conductive bonding layer.

Abstract: A method for forming a multilayer barrier comprises forming a conductive line over a substrate, depositing a dielectric layer over the conductive line, forming a plug opening in the dielectric layer, forming a multilayer barrier through a plurality of deposition processes and corresponding plasma treatment processes.