Patents by Inventor Jian-Shiou Huang
Jian-Shiou Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210305357Abstract: A structure includes a semiconductor substrate, a conductor-insulator-conductor capacitor. The conductor-insulator-conductor capacitor is disposed on the semiconductor substrate and includes a first conductor, a nitrogenous dielectric layer and a second conductor. The nitrogenous dielectric layer is disposed on the first conductor and the second conductor is disposed on the nitrogenous dielectric layer.Type: ApplicationFiled: June 14, 2021Publication date: September 30, 2021Inventors: Jian-Shiou HUANG, Chia-Shiung TSAI, Cheng-Yuan TSAI, Hsing-Lien LIN, Yao-Wen CHANG
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Patent number: 11038010Abstract: A structure includes a semiconductor substrate, a conductor-insulator-conductor capacitor. The conductor-insulator-conductor capacitor is disposed on the semiconductor substrate and includes a first conductor, a nitrogenous dielectric layer and a second conductor. The nitrogenous dielectric layer is disposed on the first conductor and the second conductor is disposed on the nitrogenous dielectric layer.Type: GrantFiled: January 29, 2015Date of Patent: June 15, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Jian-Shiou Huang, Chia-Shiung Tsai, Cheng-Yuan Tsai, Hsing-Lien Lin, Yao-Wen Chang
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Patent number: 10978305Abstract: A film stack and manufacturing method thereof are provided. The film stack includes a plurality of first metal-containing films, and a plurality of second metal-containing films. The first metal-containing films and the second metal-containing films are alternately stacked to each other. The first metal-containing films and the second metal-containing films comprise the same metal element and the same nonmetal element, and a concentration of the metal element in the second metal-containing film is greater than a concentration of the nonmetal element in the second metal-containing film.Type: GrantFiled: July 30, 2018Date of Patent: April 13, 2021Assignee: Taiwan Semiconductor Manufacturing Company Ltd.Inventors: Yao-Wen Chang, Jian-Shiou Huang, Cheng-Yuan Tsai
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Patent number: 10937686Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor device having an enhanced gap fill layer in trenches. The present disclosure provides a novel gap fill layer formed using a multi-step deposition and in-situ treatment process. The deposition process can be a flowable chemical vapor deposition (FCVD) utilizing one or more assist gases and molecules of low reactive sticking coefficient (RSC). The treatment process can be an in-situ process after the deposition process and includes exposing the deposited gap fill layer to plasma activated assist gas. The assist gas can be formed of ammonia. The low RSC molecule can be formed of trisilylamin (TSA) or perhydropolysilazane (PHPS).Type: GrantFiled: July 22, 2019Date of Patent: March 2, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jian-Shiou Huang, Bang-Tai Tang, Chih-Tang Peng, Tai-Chun Huang, Yen-Chun Huang
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Publication number: 20210020934Abstract: A positive and negative electrode material and a preparation method thereof are provided. The positive and negative electrode material includes a powder, a first seed growth layer and a second graft growth layer. A material of the powder includes graphite, silicon based material, lithium titanate, tin oxide, tin alloy, lithium nickel cobalt manganese oxide, lithium nickel cobalt aluminum oxide or lithium iron phosphate. The first seed growth layer is formed radially on a surface of the powder, and the second graft growth layer is radially connected to the first seed growth layer.Type: ApplicationFiled: July 15, 2020Publication date: January 21, 2021Applicant: GIGA SOLAR MATERIALS CORP.Inventors: Wen-Chun Yen, Wei-Hsiang Huang, Wei-Kai Liao, Jian-Shiou Huang
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Publication number: 20210020905Abstract: A lithium ion battery silicon carbon electrode material and a preparation method thereof are provided. The lithium ion battery silicon carbon electrode material includes a graphite particle and a resin carbon layer. The resin carbon layer is smoothly coated on a surface of the graphite particle, and silicon or a silicon compound and a conductive material are coated in the resin carbon layer.Type: ApplicationFiled: July 15, 2020Publication date: January 21, 2021Applicant: GIGA SOLAR MATERIALS CORP.Inventors: Meng-Ting Tsai, Jian-Shiou Huang, Chun-Wei Hsu, Wen-Chun Yen
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Publication number: 20210020909Abstract: An electrode material and a preparation method thereof are provided. The electrode material includes a particle and a charged irregular geometric porous structure disposed on the surface of the particle. A material of the particle includes silicon, silicon oxide, metal, metal oxide, carbon, graphite or a composite material thereof.Type: ApplicationFiled: July 15, 2020Publication date: January 21, 2021Applicant: GIGA SOLAR MATERIALS CORP.Inventors: Wen-Chun Yen, Jian-Shiou Huang, Chun-Wei Hsu, Pin-Shen Liou
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Patent number: 10629497Abstract: A semiconductor device structure and a method for forming the same are provided. The semiconductor device structure includes a first fin structure protruding from the first region of the semiconductor substrate and having a first portion and a second portion over the first portion. The semiconductor device structure also includes a liner structure including a first insulating liner layer and second insulating liner layer. The first insulating liner layer has a bottom portion covering the semiconductor substrate and a sidewall portion covering a sidewall of the first portion of the first fin structure. The second insulating liner layer is over the bottom portion and the sidewall portion of the first insulating liner layer and extends on a top surface of the sidewall portion of the first insulating liner layer. The semiconductor device structure also includes an isolation feature over the liner structure.Type: GrantFiled: February 22, 2018Date of Patent: April 21, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Han-Pin Chung, Jian-Shiou Huang
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Publication number: 20190341294Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor device having an enhanced gap fill layer in trenches. The present disclosure provides a novel gap fill layer formed using a multi-step deposition and in-situ treatment process. The deposition process can be a flowable chemical vapor deposition (FCVD) utilizing one or more assist gases and molecules of low reactive sticking coefficient (RSC). The treatment process can be an in-situ process after the deposition process and includes exposing the deposited gap fill layer to plasma activated assist gas. The assist gas can be formed of ammonia. The low RSC molecule can be formed of trisilylamin (TSA) or perhydropolysilazane (PHPS).Type: ApplicationFiled: July 22, 2019Publication date: November 7, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jian-Shiou Huang, Bang-Tai Tang, Chih-Tang Peng, Tai-Chun Huang, Yen-Chun Huang
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Patent number: 10468409Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a fin structure protruding from a semiconductor substrate. The fin structure includes a first portion and an overlying second portion. The first portion is formed of a material that is the same as that of the semiconductor substrate and different from that of the second portion. The semiconductor device structure also includes a liner structure and an isolation feature. The liner structure includes a carbon-doped silicon oxide film covering the semiconductor substrate and the first portion of the first fin structure and a nitrogen-containing film over the carbon-doped silicon oxide film. The isolation feature is over the nitrogen-containing film and surrounded by the liner structure.Type: GrantFiled: March 14, 2018Date of Patent: November 5, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Szu-Ping Lee, Jian-Shiou Huang, Chih-Tang Peng, Sung-En Lin
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Publication number: 20190287971Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a fin structure protruding from a semiconductor substrate. The fin structure includes a first portion and an overlying second portion. The first portion is formed of a material that is the same as that of the semiconductor substrate and different from that of the second portion. The semiconductor device structure also includes a liner structure and an isolation feature. The liner structure includes a carbon-doped silicon oxide film covering the semiconductor substrate and the first portion of the first fin structure and a nitrogen-containing film over the carbon-doped silicon oxide film. The isolation feature is over the nitrogen-containing film and surrounded by the liner structure.Type: ApplicationFiled: March 14, 2018Publication date: September 19, 2019Inventors: Szu-Ping LEE, Jian-Shiou HUANG, Chih-Tang PENG, Sung-En LIN
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Patent number: 10361113Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor device having an enhanced gap fill layer in trenches. The present disclosure provides a novel gap fill layer formed using a multi-step deposition and in-situ treatment process. The deposition process can be a flowable chemical vapor deposition (FCVD) utilizing one or more assist gases and molecules of low reactive sticking coefficient (RSC). The treatment process can be an in-situ process after the deposition process and includes exposing the deposited gap fill layer to plasma activated assist gas. The assist gas can be formed of ammonia. The low RSC molecule can be formed of trisilylamin (TSA) or perhydropolysilazane (PHPS).Type: GrantFiled: January 22, 2018Date of Patent: July 23, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jian-Shiou Huang, Bang-Tai Tang, Chih-Tang Peng, Tai-Chun Huang, Yen-Chun Huang
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Publication number: 20190131186Abstract: A semiconductor device structure and a method for forming the same are provided. The semiconductor device structure includes a first fin structure protruding from the first region of the semiconductor substrate and having a first portion and a second portion over the first portion. The semiconductor device structure also includes a liner structure including a first insulating liner layer and second insulating liner layer. The first insulating liner layer has a bottom portion covering the semiconductor substrate and a sidewall portion covering a sidewall of the first portion of the first fin structure. The second insulating liner layer is over the bottom portion and the sidewall portion of the first insulating liner layer and extends on a top surface of the sidewall portion of the first insulating liner layer. The semiconductor device structure also includes an isolation feature over the liner structure.Type: ApplicationFiled: February 22, 2018Publication date: May 2, 2019Inventors: Han-Pin CHUNG, Jian-Shiou HUANG
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Patent number: 10176999Abstract: A film stack and manufacturing method thereof are provided. The film stack includes a plurality of first metal-containing films, and a plurality of second metal-containing films. The first metal-containing films and the second metal-containing films are alternately stacked to each other. The first metal-containing films and the second metal-containing films comprise the same metal element and the same nonmetal element, and a concentration of the metal element in the second metal-containing film is greater than a concentration of the nonmetal element in the second metal-containing film.Type: GrantFiled: May 5, 2016Date of Patent: January 8, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Yao-Wen Chang, Jian-Shiou Huang, Cheng-Yuan Tsai
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Publication number: 20190006228Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor device having an enhanced gap fill layer in trenches. The present disclosure provides a novel gap fill layer formed using a multi-step deposition and in-situ treatment process. The deposition process can be a flowable chemical vapor deposition (FCVD) utilizing one or more assist gases and molecules of low reactive sticking coefficient (RSC). The treatment process can be an in-situ process after the deposition process and includes exposing the deposited gap fill layer to plasma activated assist gas. The assist gas can be formed of ammonia. The low RSC molecule can be formed of trisilylamin (TSA) or perhydropolysilazane (PHPS).Type: ApplicationFiled: January 22, 2018Publication date: January 3, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jian-Shiou Huang, Bang-Tai Tang, Chih-Tang Peng, Tai-Chun Huang, Yen-Chun Huang
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Publication number: 20180337051Abstract: A film stack and manufacturing method thereof are provided. The film stack includes a plurality of first metal-containing films, and a plurality of second metal-containing films. The first metal-containing films and the second metal-containing films are alternately stacked to each other. The first metal-containing films and the second metal-containing films comprise the same metal element and the same nonmetal element, and a concentration of the metal element in the second metal-containing film is greater than a concentration of the nonmetal element in the second metal-containing film.Type: ApplicationFiled: July 30, 2018Publication date: November 22, 2018Inventors: Yao-Wen CHANG, Jian-Shiou HUANG, Cheng-Yuan TSAI
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Patent number: 9887134Abstract: Semiconductor devices, methods of manufacture thereof, and methods of singulating semiconductor devices are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes forming a trench in a substrate, the trench being formed within a first side of the substrate and disposed around a portion of the substrate. A first insulating material is formed over the first side of the substrate and the trench, and a second insulating material is formed over the first insulating material. Apertures are formed in the second insulating material and the first insulating material over the portion of the substrate. Features are formed in the apertures, and a carrier is coupled to the features and the second insulating material. A second side of the substrate is planarized, the second side of the substrate being opposite the first side of the substrate. The second insulating material is removed, and the carrier is removed.Type: GrantFiled: June 1, 2016Date of Patent: February 6, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yao-Wen Chang, Jian-Shiou Huang, Cheng-Yuan Tsai, Kong-Beng Thei
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Patent number: 9825117Abstract: Some embodiments of the present disclosure provide an integrated circuit (IC) device including a metal-insulator-metal (MIM) capacitor structure. The MIM capacitor structure includes a lower metal capacitor electrode, an upper metal capacitor electrode, and a capacitor dielectric separating the lower metal capacitor electrode from the upper metal capacitor electrode. The capacitor dielectric is made up of an amorphous oxide/nitride matrix and a plurality of metal or metal oxide/nitride nano-particles that are randomly distributed over the volume of amorphous oxide/nitride matrix.Type: GrantFiled: December 28, 2016Date of Patent: November 21, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jian-Shiou Huang, Yao-Wen Chang, Hsing-Lien Lin, Cheng-Yuan Tsai, Chia-Shiung Tsai
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Patent number: 9761799Abstract: A method for manufacturing an integrated circuit (IC) is provided. An etch is performed into an upper surface of an insulating layer to form an opening. A plurality of electrode layers is formed filling the opening. Forming the plurality of electrode layers comprises repeatedly forming an electrode layer conformally lining an unfilled region of the opening until the opening is filled. Forming the electrode layer comprises depositing the electrode layer and treating a surface of the electrode layer that faces an interior of the opening. A planarization is performed into the plurality of electrode layers to the upper surface of the insulating layer.Type: GrantFiled: September 20, 2016Date of Patent: September 12, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jian-Shiou Huang, Cheng-Yuan Tsai, Yao-Wen Chang
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Publication number: 20170229346Abstract: Semiconductor devices, methods of manufacture thereof, and methods of singulating semiconductor devices are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes forming a trench in a substrate, the trench being formed within a first side of the substrate and disposed around a portion of the substrate. A first insulating material is formed over the first side of the substrate and the trench, and a second insulating material is formed over the first insulating material. Apertures are formed in the second insulating material and the first insulating material over the portion of the substrate. Features are formed in the apertures, and a carrier is coupled to the features and the second insulating material. A second side of the substrate is planarized, the second side of the substrate being opposite the first side of the substrate. The second insulating material is removed, and the carrier is removed.Type: ApplicationFiled: June 1, 2016Publication date: August 10, 2017Inventors: Yao-Wen Chang, Jian-Shiou Huang, Cheng-Yuan Tsai, Kong-Beng Thei