Abstract: A method includes designing a plurality of cells for a semiconductor device, wherein designing the plurality of cells comprises reserving a routing track of a plurality of routing tracks within each of the plurality of cells, wherein each of the plurality of cells comprises signal lines, and the reserved routing track is free of the signal lines. The method includes placing a first cell and a second cell of the plurality of cells in a layout of the semiconductor device. The method includes determining whether any power rails overlap with any of the plurality of routing tracks other than the reserved routing track in the second cell. The method includes adjusting a distance between the first cell and the second cell in response to a determination that at least one power rail overlaps with at least one routing track other than the reserved routing track.

Abstract: A multiplexer circuit includes first and second fins each extending in an X-axis direction. First, second, third and fourth gates extend in a Y-axis direction perpendicular to the X-axis direction and contact the first and second fins. The first, second, third and fourth gates are configured to receive first, second, third and fourth data signals, respectively. Fifth, sixth, seventh and eighth gates extend in the Y-axis direction and contact the first and second fins, the fifth, sixth, seventh and eighth gates, and are configured to receive the first, second, third and fourth select signals, respectively. An input logic circuit is configured to provide an output at an intermediate node. A ninth gate extends in the Y-axis direction and contacts the first and second fins. An output logic circuit is configured to provide a selected one of the first, second, third and fourth data signals at an output terminal.

Abstract: A multiplexer circuit includes first and second fins each extending in an X-axis direction. First, second, third and fourth gates extend in a Y-axis direction perpendicular to the X-axis direction and contact the first and second fins. The first, second, third and fourth gates are configured to receive first, second, third and fourth data signals, respectively. Fifth, sixth, seventh and eighth gates extend in the Y-axis direction and contact the first and second fins, the fifth, sixth, seventh and eighth gates, and are configured to receive the first, second, third and fourth select signals, respectively. An input logic circuit is configured to provide an output at an intermediate node. A ninth gate extends in the Y-axis direction and contacts the first and second fins. An output logic circuit is configured to provide a selected one of the first, second, third and fourth data signals at an output terminal.

Abstract: A method includes designing a plurality of cells for a semiconductor device, wherein designing the plurality of cells comprises reserving a routing track of a plurality of routing tracks within each of the plurality of cells, wherein each of the plurality of cells comprises signal lines, and the reserved routing track is free of the signal lines. The method includes placing a first cell and a second cell of the plurality of cells in a layout of the semiconductor device. The method includes determining whether any power rails overlap with any of the plurality of routing tracks other than the reserved routing track in the second cell. The method includes adjusting a distance between the first cell and the second cell in response to a determination that at least one power rail overlaps with at least one routing track other than the reserved routing track.

Abstract: A semiconductor device includes first and second gate structures, a metallization layer, and first and second tie-off contacts. The first and second gate structures extend substantially along a first direction and are aligned with each other substantially along the first direction. The metallization layer includes a Vdd line, a Vss line, metal lines between the Vdd line and the Vss line and extending substantially along a second direction different from the first direction. The first tie-off contact overlaps an intersection of the first gate structure and a first one of the Vdd line and the Vss line from a top view. The second tie-off contact overlaps an intersection of the second gate structure and a first one of the metal lines from the top view, wherein said first one of the metal lines is adjacent to a second one of the Vdd line and the Vss line.

Abstract: A method includes creating a layout design of the integrated circuit after determining a difference between the poly extension effect of a p-type transistor and the poly extension effect of an n-type transistor. Creating the layout design includes forming first-type active zone patterns, forming second-type active zone patterns, generating a gate-strip pattern, and positioning the gate-strip pattern over the first-type active zone patterns and the second-type active zone patterns. Creating the layout design also includes determining whether to generate one or more poly cut patterns that intersect the gate-strip, based on the difference between the poly extension effect of a p-type transistor and the poly extension effect of an n-type transistor.

Abstract: A multiplexer circuit includes first and second fins each extending in an X-axis direction. First, second, third and fourth gates extend in a Y-axis direction perpendicular to the X-axis direction and contact the first and second fins. The first, second, third and fourth gates are configured to receive first, second, third and fourth data signals, respectively. Fifth, sixth, seventh and eighth gates extend in the Y-axis direction and contact the first and second fins, the fifth, sixth, seventh and eighth gates, and are configured to receive the first, second, third and fourth select signals, respectively. An input logic circuit is configured to provide an output at an intermediate node. A ninth gate extends in the Y-axis direction and contacts the first and second fins. An output logic circuit is configured to provide a selected one of the first, second, third and fourth data signals at an output terminal.

Abstract: An integrated circuit includes a first transistor of a first conductivity type including a first active area extending in a first direction; a second transistor of the first conductivity type including at least two second active areas extending in the first direction and a first gate stripe crossing the at least two second active areas; and a third transistor of a second conductivity type that is stacked on the second transistor and includes at least two third active areas arranged above the at least two second active areas. A top most boundary line of the first active area is aligned with a top most boundary line of one of the at least two third active areas in a layout view.

Abstract: A method of fabricating an integrated circuit. The method includes generating two first-type active zones and two second-type active zones, and generating a gate-strip intersecting the two first-type active zones and the two second-type active zones. The method further includes patterning one or more poly cuts intersecting the gate-strip based on a determination of a difference between the poly extension effect of a p-type transistor and the poly extension effect of an n-type transistor.

Abstract: A method includes reserving a routing track within a cell, wherein the cell comprises signal lines for connection to elements within the cell, the cell further comprises a plurality of routing tracks, the reserved routing track is one of the plurality of routing tracks, and the reserved routing track is free of the signal lines. The method further includes determining whether any power rails overlap with any of the plurality of routing tracks other than the reserved routing track. The method further includes adjusting a position of the cell in response to a determination that at least one power rail overlaps with at least one routing track of the plurality of routing tracks other than the reserved routing track.

Abstract: A method of forming an integrated circuit (IC) includes generating a netlist of a first circuit, generating a first cell layout of the first circuit, placing the first cell layout, by an automatic placement and routing (APR) tool, in a first region of a layout design. The first circuit is configured as a non-functional circuit. The first circuit includes a first pin and a second pin that are electrically disconnected from each other. Generating the netlist of the first circuit includes designating the first pin and the second pin as a first group of pins that are to be connected together. Placing the first cell layout by the APR tool includes connecting the first pin and the second pin in the first group of pins together thereby changing the first circuit to a second circuit. The second circuit is configured as a functional version of the first circuit.

Abstract: An integrated circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. The first transistor includes a first active area extending in a first direction in a first layer. The second transistor includes a second active area that is disposed in a second layer below the first layer and overlaps the first active area. The third transistor includes at least two third active areas extending in the first direction in the first layer. In the first direction, a boundary line of one of the at least two third active areas is aligned with boundary lines of the first and second active areas. The fourth transistor includes at least two fourth active areas that are disposed in the second layer and overlap the at least two third active areas.

Abstract: A multiplexer circuit includes first and second fins each extending in an X-axis direction. First, second, third and fourth gates extend in a Y-axis direction perpendicular to the X-axis direction and contact the first and second fins. The first, second, third and fourth gates are configured to receive first, second, third and fourth data signals, respectively. Fifth, sixth, seventh and eighth gates extend in the Y-axis direction and contact the first and second fins, the fifth, sixth, seventh and eighth gates, and are configured to receive the first, second, third and fourth select signals, respectively. An input logic circuit is configured to provide an output at an intermediate node. A ninth gate extends in the Y-axis direction and contacts the first and second fins. An output logic circuit is configured to provide a selected one of the first, second, third and fourth data signals at an output terminal.

Abstract: A method includes positioning a first active region adjacent to a pair of second active regions in an initial integrated circuit (IC) layout diagram of an initial cell, to align side edges of the first active region and corresponding side edges of each second active region of the pair of second active regions along a cell height direction. The first active region forms, together with the initial cell, a modified cell having a modified IC layout diagram. The side edges of the first active region and the corresponding side edges of each second active region extend along the cell height direction. A height dimension of the first active region in the cell height direction is less than half of a height dimension of each second active region of the pair of second active regions in the cell height direction. The positioning the first active region is executed by a processor.

Abstract: A method of fabricating an integrated circuit. The method includes generating two first-type active zones and two second-type active zones, and generating a gate-strip intersecting the two first-type active zones and the two second-type active zones. The method further includes patterning one or more poly cuts intersecting the gate-strip based on a determination of a difference between the poly extension effect of a p-type transistor and the poly extension effect of an n-type transistor.

Abstract: A multiplexer circuit includes first and second fins each extending in an X-axis direction. First, second, third and fourth gates extend in a Y-axis direction perpendicular to the X-axis direction and contact the first and second fins. The first, second, third and fourth gates are configured to receive first, second, third and fourth data signals, respectively. Fifth, sixth, seventh and eighth gates extend in the Y-axis direction and contact the first and second fins, the fifth, sixth, seventh and eighth gates, and are configured to receive the first, second, third and fourth select signals, respectively. An input logic circuit is configured to provide an output at an intermediate node. A ninth gate extends in the Y-axis direction and contacts the first and second fins. An output logic circuit is configured to provide a selected one of the first, second, third and fourth data signals at an output terminal.

Abstract: A multiplexer circuit includes first and second fins each extending in an X-axis direction. First, second, third and fourth gates extend in a Y-axis direction perpendicular to the X-axis direction and contact the first and second fins. The first, second, third and fourth gates are configured to receive first, second, third and fourth data signals, respectively. Fifth, sixth, seventh and eighth gates extend in the Y-axis direction and contact the first and second fins, the fifth, sixth, seventh and eighth gates, and are configured to receive the first, second, third and fourth select signals, respectively. An input logic circuit is configured to provide an output at an intermediate node. A ninth gate extends in the Y-axis direction and contacts the first and second fins. An output logic circuit is configured to provide a selected one of the first, second, third and fourth data signals at an output terminal.

Abstract: An integrated circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. The first transistor includes a first active area extending in a first direction in a first layer. The second transistor includes a second active area that is disposed in a second layer below the first layer and overlaps the first active area. The third transistor includes at least two third active areas extending in the first direction in the first layer. In the first direction, a boundary line of one of the at least two third active areas is aligned with boundary lines of the first and second active areas. The fourth transistor includes at least two fourth active areas that are disposed in the second layer and overlap the at least two third active areas.

Abstract: A method includes reserving a routing track within a cell, wherein the cell comprises signal lines for connection to elements within the cell, the cell further comprises a plurality of routing tracks, the reserved routing track is one of the plurality of routing tracks, and the reserved routing track is free of the signal lines. The method further includes determining whether any power rails overlap with any of the plurality of routing tracks other than the reserved routing track. The method further includes adjusting a position of the cell in response to a determination that at least one power rail overlaps with at least one routing track of the plurality of routing tracks other than the reserved routing track.

Abstract: An integrated circuit includes a first cell and a second cell. The first cell with a first cell height along a first direction includes a first active region and a second active region that extend in a second direction different from the first direction. The first active region overlaps the second active region in a layout view. The second cell with a second cell height includes a first plurality of active regions and a second plurality of active regions. The first plurality of active regions and the second plurality of active regions extend in the second direction and the first plurality of active regions overlap the second plurality of active regions, respectively, in the layout view. The first cell abuts the second cell, and the first active region is aligned with one of the first plurality of active regions in the layout view.