Patents by Inventor Jian-Ting Chen
Jian-Ting Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11955154Abstract: A sense amplifier circuit includes a sense amplifier, a switch and a temperature compensation circuit. The temperature compensation circuit provides a control signal having a positive temperature coefficient, based on which the switch provides reference impedance for temperature compensation. The sense amplifier includes a first input end coupled to a target bit and a second input end coupled to the switch. The sense amplifier outputs a sense amplifier signal based on the reference impedance and the impedance of the target bit.Type: GrantFiled: May 16, 2022Date of Patent: April 9, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Cheng-Tung Huang, Jen-Yu Wang, Po-Chun Yang, Yi-Ting Wu, Yung-Ching Hsieh, Jian-Jhong Chen, Chia-Wei Lee
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Patent number: 11942130Abstract: A bottom-pinned spin-orbit torque magnetic random access memory (SOT-MRAM) is provided in the present invention, including a substrate, a bottom electrode layer on the substrate, a magnetic tunnel junction (MTJ) on the bottom electrode layer, a spin-orbit torque (SOT) layer on the MTJ, a capping layer on the SOT layer, and an injection layer on the capping layer, wherein the injection layer is divided into individual first part and second part, and the first part and the second part are connected respectively with two ends of the capping layer.Type: GrantFiled: March 23, 2022Date of Patent: March 26, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Jian-Jhong Chen, Yi-Ting Wu, Jen-Yu Wang, Cheng-Tung Huang, Po-Chun Yang, Yung-Ching Hsieh
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Patent number: 11939603Abstract: A modified cutinase is disclosed. The cutinase has the modified amino acid sequence of SEQ ID NO: 2, wherein the modification is a substitution of asparagine at position 181 with alanine, or substitutions of asparagine at position 181 with alanine and phenylalanine at position 235 with leucine. The modified enzyme has improved PET-hydrolytic activity, and thus, the high-activity PET hydrolase is obtained, and the industrial application value of the PET hydrolase is enhanced.Type: GrantFiled: June 21, 2023Date of Patent: March 26, 2024Assignee: HUBEI UNIVERSITYInventors: Chun-Chi Chen, Jian-Wen Huang, Jian Min, Xian Li, Beilei Shi, Panpan Shen, Yu Yang, Yumei Hu, Longhai Dai, Lilan Zhang, Yunyun Yang, Rey-Ting Guo
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Publication number: 20230363080Abstract: A semiconductor package assembly includes a circuit board, a heat dissipating element and a semiconductor device. The circuit board includes a conductive pattern. The heat dissipating element is located on the circuit board, where the heat dissipating element is connected to the conductive pattern. The semiconductor device is located on the circuit board and next to the heat dissipating element, where the semiconductor device is thermally connected to the heat dissipating element through the conductive pattern.Type: ApplicationFiled: July 14, 2023Publication date: November 9, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jian-Ting Chen, Cheng-Wei Lu, Kuang-Hua Wang
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Patent number: 11805644Abstract: Provided is a manufacturing method of a memory device, including: forming a stacked layer on a substrate; patterning the stacked layer to form a plurality of openings in the stacked layer; forming a spacer on a sidewall of the openings; performing a first etching process by using the spacer as a mask to form a plurality of stack structures, wherein the spacer is embedded in the stack structures, such that a width of an upper portion of the stack structures is less than a width of a lower portion thereof; forming a dielectric layer on the stack structures and the spacer; and respectively forming a plurality of contact plugs on the substrate between the stack structures.Type: GrantFiled: January 3, 2022Date of Patent: October 31, 2023Assignee: Winbond Electronics Corp.Inventors: Jian-Ting Chen, Yao-Ting Tsai, Hsiu-Han Liao
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Patent number: 11778727Abstract: A semiconductor package assembly includes a circuit board, a heat dissipating element and a semiconductor device. The circuit board includes a conductive pattern. The heat dissipating element is located on the circuit board, where the heat dissipating element is connected to the conductive pattern. The semiconductor device is located on the circuit board and next to the heat dissipating element, where the semiconductor device is thermally connected to the heat dissipating element through the conductive pattern.Type: GrantFiled: August 30, 2021Date of Patent: October 3, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jian-Ting Chen, Cheng-Wei Lu, Kuang-Hua Wang
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Publication number: 20230280370Abstract: A testing apparatus for a semiconductor package includes a circuit board, testing patterns and a socket. The circuit board has a testing region and includes a plurality of testing contacts and a plurality of signal contacts distributed in the testing region. The testing patterns are embedded in the circuit board and electrically connected to the testing contacts, where each of the testing patterns includes a first conductive line and a second conductive line including a main portion and a branch portion connected to main portion. The first conductive line is connected to the main portion. The socket is located on the circuit board and comprising connectors electrically connected to the circuit board, wherein the connectors are configured to transmit electric signals for testing the semiconductor package from the testing apparatus.Type: ApplicationFiled: May 11, 2023Publication date: September 7, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jian-Ting Chen, Cheng-Han Huang, Kuang-Hua Wang
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Patent number: 11693025Abstract: A testing apparatus for a semiconductor package includes a circuit board, testing patterns and a socket. The circuit board has a testing region and includes a plurality of testing contacts and a plurality of signal contacts distributed in the testing region. The testing patterns are embedded in the circuit board and electrically connected to the testing contacts, where each of the testing patterns includes a first conductive line and a second conductive line including a main portion and a branch portion connected to main portion. The first conductive line is connected to the main portion. The socket is located on the circuit board and comprising connectors electrically connected to the circuit board, wherein the connectors are configured to transmit electric signals for testing the semiconductor package from the testing apparatus.Type: GrantFiled: August 30, 2021Date of Patent: July 4, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jian-Ting Chen, Cheng-Han Huang, Kuang-Hua Wang
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Publication number: 20230066017Abstract: A semiconductor package assembly includes a circuit board, a heat dissipating element and a semiconductor device. The circuit board includes a conductive pattern. The heat dissipating element is located on the circuit board, where the heat dissipating element is connected to the conductive pattern. The semiconductor device is located on the circuit board and next to the heat dissipating element, where the semiconductor device is thermally connected to the heat dissipating element through the conductive pattern.Type: ApplicationFiled: August 30, 2021Publication date: March 2, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jian-Ting Chen, Cheng-Wei Lu, Kuang-Hua Wang
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Publication number: 20230067209Abstract: A testing apparatus for a semiconductor package includes a circuit board, testing patterns and a socket. The circuit board has a testing region and includes a plurality of testing contacts and a plurality of signal contacts distributed in the testing region. The testing patterns are embedded in the circuit board and electrically connected to the testing contacts, where each of the testing patterns includes a first conductive line and a second conductive line including a main portion and a branch portion connected to main portion. The first conductive line is connected to the main portion. The socket is located on the circuit board and comprising connectors electrically connected to the circuit board, wherein the connectors are configured to transmit electric signals for testing the semiconductor package from the testing apparatus.Type: ApplicationFiled: August 30, 2021Publication date: March 2, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jian-Ting Chen, Cheng-Han Huang, Kuang-Hua Wang
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Publication number: 20230017264Abstract: Provided is a semiconductor device including a substrate, multiple first gate structures, and a protective structure. The substrate includes a first region and a second region. The first gate structures are disposed on the substrate in the first region. The protective structure conformally covers a sidewall of one of the first gate structures adjacent to the second region. The protective structure includes a lower portion and an upper portion disposed on the lower portion. The lower portion and the upper portion have different dielectric materials. A method of forming a semiconductor device is also provided.Type: ApplicationFiled: July 14, 2021Publication date: January 19, 2023Applicant: Winbond Electronics Corp.Inventors: Yu-Lung Wang, Yao-Ting Tsai, Jian-Ting Chen, Yuan-Huang Wei
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Patent number: 11362098Abstract: A method for manufacturing a memory device is provided. The method includes the following steps: providing a substrate; forming a plurality of first gate structures; forming a lining layer on the substrate; forming a spacer layer on the lining layer; forming a stop layer on the spacer layer; forming a first sacrificial layer on the stop layer; removing a portion of the first sacrificial layer to expose the stop layer on the first gate structures, and to expose the stop layer at the bottoms of the trenches; removing the stop layer at the bottoms of the trenches to expose the spacer layer; removing the remaining first sacrificial layer; forming a second sacrificial layer on the substrate; and removing the second sacrificial layer, and removing the spacer layer and the lining layer at the bottoms of the plurality of trenches to expose the substrate.Type: GrantFiled: October 1, 2020Date of Patent: June 14, 2022Assignee: WINBOND ELECTRONICS CORP.Inventors: Che-Fu Chuang, Jian-Ting Chen, Yu-Kai Liao, Hsiu-Han Liao
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Publication number: 20220123007Abstract: Provided is a manufacturing method of a memory device, including: forming a stacked layer on a substrate; patterning the stacked layer to form a plurality of openings in the stacked layer; forming a spacer on a sidewall of the openings; performing a first etching process by using the spacer as a mask to form a plurality of stack structures, wherein the spacer is embedded in the stack structures, such that a width of an upper portion of the stack structures is less than a width of a lower portion thereof; forming a dielectric layer on the stack structures and the spacer; and respectively forming a plurality of contact plugs on the substrate between the stack structures.Type: ApplicationFiled: January 3, 2022Publication date: April 21, 2022Applicant: Winbond Electronics Corp.Inventors: Jian-Ting Chen, Yao-Ting Tsai, Hsiu-Han Liao
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Patent number: 11257833Abstract: Provided is a memory device including a substrate, a plurality of stack structures, a spacer, a dielectric layer, and a plurality of contact plugs. The stack structures are disposed on the substrate. The spacer is embedded in the stack structures, so that a width of an upper portion of the stack structures is less than a width of a lower portion thereof. The dielectric layer conformally covers the stack structures and the spacer. The contact plugs are respectively disposed on the substrate between the stack structures.Type: GrantFiled: September 12, 2019Date of Patent: February 22, 2022Assignee: Winbond Electronics Corp.Inventors: Jian-Ting Chen, Yao-Ting Tsai, Hsiu-Han Liao
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Patent number: 11251273Abstract: A non-volatile memory device and its manufacturing method are provided. The method includes the following steps. A plurality of isolation structures are formed in a substrate. A first polycrystalline silicon layer is formed in the substrate and between two adjacent isolation structures. A first implantation process is performed to implant a first dopant into the first polycrystalline silicon layer and the isolation structures. A portion of each of the isolation structures is partially removed, and the remaining portion of each of the isolation structures has a substantially flat top surface. An annealing process is performed after partially removing the isolation structures to uniformly diffuse the first dopant in the first polycrystalline silicon layer. A dielectric layer is formed on the first polycrystalline silicon layer, and a second polycrystalline silicon layer is formed on the dielectric layer.Type: GrantFiled: July 24, 2019Date of Patent: February 15, 2022Assignee: Winbond Electronics Corp.Inventors: Jian-Ting Chen, Yao-Ting Tsai, Jung-Ho Chang, Hsiu-Han Liao
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Publication number: 20210151447Abstract: A method for manufacturing a memory device is provided. The method includes the following steps: providing a substrate; forming a plurality of first gate structures; forming a lining layer on the substrate; forming a spacer layer on the lining layer; forming a stop layer on the spacer layer; forming a first sacrificial layer on the stop layer; removing a portion of the first sacrificial layer to expose the stop layer on the first gate structures, and to expose the stop layer at the bottoms of the trenches; removing the stop layer at the bottoms of the trenches to expose the spacer layer; removing the remaining first sacrificial layer; forming a second sacrificial layer on the substrate; and removing the second sacrificial layer, and removing the spacer layer and the lining layer at the bottoms of the plurality of trenches to expose the substrate.Type: ApplicationFiled: October 1, 2020Publication date: May 20, 2021Inventors: Che-Fu CHUANG, Jian-Ting CHEN, Yu-Kai LIAO, Hsiu-Han LIAO
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Publication number: 20200273871Abstract: Provided is a memory device including a substrate, a plurality of stack structures, a spacer, a dielectric layer, and a plurality of contact plugs. The stack structures are disposed on the substrate. The spacer is embedded in the stack structures, so that a width of an upper portion of the stack structures is less than a width of a lower portion thereof. The dielectric layer conformally covers the stack structures and the spacer. The contact plugs are respectively disposed on the substrate between the stack structures.Type: ApplicationFiled: September 12, 2019Publication date: August 27, 2020Applicant: Winbond Electronics Corp.Inventors: Jian-Ting Chen, Yao-Ting Tsai, Hsiu-Han Liao
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Publication number: 20200035794Abstract: A non-volatile memory device and its manufacturing method are provided. The method includes the following steps. A plurality of isolation structures are formed in a substrate. A first polycrystalline silicon layer is formed in the substrate and between two adjacent isolation structures. A first implantation process is performed to implant a first dopant into the first polycrystalline silicon layer and the isolation structures. A portion of each of the isolation structures is partially removed, and the remaining portion of each of the isolation structures has a substantially flat top surface. An annealing process is performed after partially removing the isolation structures to uniformly diffuse the first dopant in the first polycrystalline silicon layer. A dielectric layer is formed on the first polycrystalline silicon layer, and a second polycrystalline silicon layer is formed on the dielectric layer.Type: ApplicationFiled: July 24, 2019Publication date: January 30, 2020Inventors: Jian-Ting CHEN, Yao-Ting TSAI, Jung-Ho CHANG, Hsiu-Han LIAO
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Patent number: 8285355Abstract: A biomedical electric wave sensor includes a base, a central pole, a dry electrode, a case, and a plurality of ribs. When the central pole lowers down, the ribs radiate and expand outward to push aside the hair of a subject, and the dry electrode exposes from the case and contacts the skin of the subject to measure a physiological electric wave signal from the subject. The present invention may overcome the intervention problem caused by hair and achieve the measurement of biomedical electric wave signal.Type: GrantFiled: May 12, 2010Date of Patent: October 9, 2012Assignee: National Chiao Tung UniversityInventors: Yu-Han Chen, Paul C.-P. Chao, Lun-De Liao, Chin-Teng Lin, Jian-Ting Chen
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Patent number: 8144132Abstract: A multi-point sensing method used in a capacitive touch panel is disclosed to detect the voltage variation of every electrode patterned on two parallel electrode layers by means of a capacitive sensing circuit, and measure the vertical capacitance at the intersection crossed by the electrodes of the two electrode layers where the voltage variation is detected, and then compare the vertical capacitance thus measured with the initial vertical capacitance at the same intersection before touch, as a result, the intersection corresponding to the measured vertical capacitance can be determined as the touch point when the comparison result shows different.Type: GrantFiled: December 29, 2008Date of Patent: March 27, 2012Assignee: National Chiao Tung UniversityInventors: Jian Ting Chen, Paul C. P. Chao, Jyun-Yao Ruan