Patents by Inventor Jian-Wei Hong

Jian-Wei Hong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240047417
    Abstract: A method includes attaching a first die and a second die to a first wafer, the first wafer comprising: a first carrier substrate; and a first interconnect structure comprising first dielectric layers and first conductive features embedded in the first dielectric layers; attaching a third die to the first die and a fourth die to the second die; attaching a second wafer to the third die and the fourth die, the second wafer comprising: a second carrier substrate; and a second interconnect structure comprising second dielectric layers and second conductive features embedded in the second dielectric layers; removing the first carrier substrate; patterning the first dielectric layers to expose conductive features of the first die and the second die; and forming external connectors through the first dielectric layers, the external connectors being electrically connected to corresponding ones of the conductive features of the first die and the second die.
    Type: Application
    Filed: August 5, 2022
    Publication date: February 8, 2024
    Inventors: Der-Chyang Yeh, Sung-Feng Yeh, Jian-Wei Hong
  • Publication number: 20240030186
    Abstract: A manufacturing method of a package is provided. The method includes the following steps. A wafer substrate having first bonding pads is provided. A die is placed on the wafer substrate, wherein the die comprises second bonding pads bonded to the first bonding pads. The die is encapsulated by an etch stop layer and a first encapsulant. A redistribution structure is disposed over the die, the etch stop layer and the first encapsulant. A portion of the redistribution structure is removed to expose the first encapsulant. The first encapsulant is removed to expose the etch stop layer. A dielectric structure is disposed over the exposed etch stop layer and laterally encapsulates the die and the redistribution structure.
    Type: Application
    Filed: July 25, 2022
    Publication date: January 25, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Der-Chyang Yeh, Sung-Feng Yeh, Jian-Wei Hong
  • Publication number: 20230335534
    Abstract: In an embodiment, a device includes: a first integrated circuit die; a second integrated circuit die bonded to the first integrated circuit die in a face-to-back manner; a dummy semiconductor feature adjacent the second integrated circuit die and bonded to the first integrated circuit die; a support substrate attached to the dummy semiconductor feature and the second integrated circuit die; and a passivation layer extending along a top surface of the support substrate, an outer sidewall of the dummy semiconductor feature, an outer sidewall of the first integrated circuit die, and a top surface of the first integrated circuit die.
    Type: Application
    Filed: July 15, 2022
    Publication date: October 19, 2023
    Inventors: Der-Chyang Yeh, Sung-Feng Yeh, Jian-Wei Hong
  • Publication number: 20230298973
    Abstract: A package includes a semiconductor carrier, a first die, a second die, a redistribution structure, and an electron transmission path. The first die is disposed over the semiconductor carrier. The second die is stacked on the first die. The redistribution structure is over the second die. The electron transmission path extends from the semiconductor carrier to the redistribution structure. The electron transmission path is electrically connected to a ground voltage. A first portion of the electron transmission path is embedded in the semiconductor carrier, a second portion of the electron transmission path is aside the first die, and a third portion of the electron transmission path is aside the second die.
    Type: Application
    Filed: May 29, 2023
    Publication date: September 21, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Sung-Feng Yeh, Jian-Wei Hong
  • Patent number: 11699638
    Abstract: A package includes a semiconductor carrier, a first die, a second die, a first encapsulant, a second encapsulant, and an electron transmission path. The first die is disposed over the semiconductor carrier. The second die is stacked on the first die. The first encapsulant laterally encapsulates the first die. The second encapsulant laterally encapsulates the second die. The electron transmission path is electrically connected to a ground voltage. A first portion of the electron transmission path is embedded in the semiconductor carrier, a second portion of the electron transmission path is aside the first die and penetrates through the first encapsulant, and a third portion of the electron transmission path is aside the second die and penetrates through the second encapsulant.
    Type: Grant
    Filed: January 17, 2022
    Date of Patent: July 11, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Sung-Feng Yeh, Jian-Wei Hong
  • Publication number: 20220271012
    Abstract: A manufacturing method of a package includes at least the following steps. Contact vias are embedded in a semiconductor carrier. The contact vias are electrically grounded. A first die and a first encapsulant are provided over the semiconductor carrier. The first encapsulant encapsulates the first die. First through insulating vias (TIV) are formed aside the first die. The first TIVs are electrically grounded through the contact vias. The first die, the first encapsulant, and the first TIVs are grinded. A second die is stacked over the first die.
    Type: Application
    Filed: May 9, 2022
    Publication date: August 25, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Sung-Feng Yeh, Jian-Wei Hong
  • Patent number: 11373981
    Abstract: A package includes a first die, a second die, a first encapsulant, first through insulating vias (TIV), a second encapsulant, and second TIVs. The second die is stacked on the first die. The first encapsulant laterally encapsulates the first die. The first TIVs are aside the first die. The first TIVs penetrate through the first encapsulant and are electrically floating. The second encapsulant laterally encapsulates the second die. The second TIVs are aside the second die. The second TIVs penetrate through the second encapsulant and are electrically floating. The second TIVs are substantially aligned with the first TIVs.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: June 28, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Sung-Feng Yeh, Jian-Wei Hong
  • Publication number: 20220139807
    Abstract: A package includes a semiconductor carrier, a first die, a second die, a first encapsulant, a second encapsulant, and an electron transmission path. The first die is disposed over the semiconductor carrier. The second die is stacked on the first die. The first encapsulant laterally encapsulates the first die. The second encapsulant laterally encapsulates the second die. The electron transmission path is electrically connected to a ground voltage. A first portion of the electron transmission path is embedded in the semiconductor carrier, a second portion of the electron transmission path is aside the first die and penetrates through the first encapsulant, and a third portion of the electron transmission path is aside the second die and penetrates through the second encapsulant.
    Type: Application
    Filed: January 17, 2022
    Publication date: May 5, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Sung-Feng Yeh, Jian-Wei Hong
  • Patent number: 11227812
    Abstract: A package includes a semiconductor carrier, a first die, a second die, a first encapsulant, a second encapsulant, a first through insulating via (TIV), and a second TIV. The semiconductor carrier has a contact via embedded therein. The contact via is electrically grounded. The first die is disposed over the semiconductor carrier. The second die is stacked on the first die. The first encapsulant laterally encapsulates the first die. The second encapsulant laterally encapsulates the second die. The first TIV is aside the first die. The first TIV penetrates through the first encapsulant and is electrically connected to the contact via. The second TIV is aside the second die. The second TIV penetrates through the second encapsulant and is electrically connected to the contact via and the first TIV.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: January 18, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Sung-Feng Yeh, Jian-Wei Hong
  • Publication number: 20210066248
    Abstract: A package includes a first die, a second die, a first encapsulant, first through insulating vias (TIV), a second encapsulant, and second TIVs. The second die is stacked on the first die. The first encapsulant laterally encapsulates the first die. The first TIVs are aside the first die. The first TIVs penetrate through the first encapsulant and are electrically floating. The second encapsulant laterally encapsulates the second die. The second TIVs are aside the second die. The second TIVs penetrate through the second encapsulant and are electrically floating. The second TIVs are substantially aligned with the first TIVs.
    Type: Application
    Filed: February 10, 2020
    Publication date: March 4, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Fa Chen, Sung-Feng Yeh, Jian-Wei Hong
  • Publication number: 20210066168
    Abstract: A package includes a semiconductor carrier, a first die, a second die, a first encapsulant, a second encapsulant, a first through insulating via (TIV), and a second TIV. The semiconductor carrier has a contact via embedded therein. The contact via is electrically grounded. The first die is disposed over the semiconductor carrier. The second die is stacked on the first die. The first encapsulant laterally encapsulates the first die. The second encapsulant laterally encapsulates the second die. The first TIV is aside the first die. The first TIV penetrates through the first encapsulant and is electrically connected to the contact via. The second TIV is aside the second die. The second TIV penetrates through the second encapsulant and is electrically connected to the contact via and the first TIV.
    Type: Application
    Filed: January 17, 2020
    Publication date: March 4, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Fa Chen, Sung-Feng Yeh, Jian-Wei Hong