Patents by Inventor Jian Wei Sun

Jian Wei Sun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11450770
    Abstract: Embodiments of counter-stress structures and methods for forming the same are disclosed. The present disclosure describes a semiconductor wafer including a substrate having a dielectric layer formed thereon and a device region in the dielectric layer. The device region includes at least one semiconductor device. The semiconductor wafer further includes a sacrificial region adjacent to the device region, wherein the sacrificial region includes at least one counter-stress structure configured to counteract wafer stress formed in the device region.
    Type: Grant
    Filed: November 2, 2020
    Date of Patent: September 20, 2022
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Jian Hua Sun, Sizhe Li, Ji Xia, Qinxiang Wei
  • Publication number: 20220252841
    Abstract: A lens assembly includes a first lens, a second lens, a third lens, a fourth lens, a fifth lens, and a sixth lens. The first lens is with positive refractive power and includes a convex surface facing an object side. The second lens is with negative refractive power. The third lens is a biconvex lens with positive refractive power and includes a convex surface facing the object side and another convex surface facing an image side. The fourth lens is with negative refractive power. The fifth lens is with positive refractive power. The sixth lens is with positive refractive power and includes a convex surface facing the image side. The first lens, the second lens, the third lens, the fourth lens, the fifth lens, and the sixth lens are arranged in order from the object side to the image side along an optical axis.
    Type: Application
    Filed: January 10, 2022
    Publication date: August 11, 2022
    Inventors: Jian-Wei LEE, Chia-Hung SUN, Jia-Sin CHEN
  • Patent number: 11216189
    Abstract: A non-transitory computer-readable storage medium, a method, and an apparatus for reading partial data of a page on multiple data planes are provided. A processor core when loading and executing program code is arranged operably to: select at least two flash-memory access commands, which individually reads data whose length (e.g., 4KB or 8KB) is shorter than a length (e.g., 16KB) of one page across data planes for a logical unit number (LUN) according to the content of scheduling table; integrate the selected flash-memory access commands into one MPR-Lite command; drive a flash interface to perform a multi-page read lite (MPR-Lite) operation by executing the MPR-Lite command rather than the flash-memory access commands to read data from the LUN; and reply with read data to a host. Therefore, the time delay between the execution of selected flash-memory access commands would be reduced.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: January 4, 2022
    Assignee: SILICON MOTION, INC.
    Inventors: Kuan-Te Li, Jian-Wei Sun, Ting-Heng Chou
  • Patent number: 11210226
    Abstract: A data storage device is provided. The data storage device includes a flash memory, a dynamic random access memory (DRAM), and a memory controller. The flash memory is configured to store a logical-to-physical mapping (L2P) table that is divided into a plurality of group-mapping (G2P) tables. The memory controller includes a first processing core and a second processing core. The first processing core receives a host access command from a host. When a specific G2P table corresponding to a specific logical address in the host access command is not stored in the DRAM, the first processing core determines whether the second processing core has loaded the specific G2P table from the flash memory to the DRAM according to the values in a first column in a first bit map and in a second column of a second bit map.
    Type: Grant
    Filed: April 17, 2020
    Date of Patent: December 28, 2021
    Assignee: SILICON MOTION, INC.
    Inventors: Jui-Lin Yen, Sheng-Hsun Lin, Jian-Wei Sun
  • Patent number: 11086798
    Abstract: The invention introduces a method for controlling data access to a flash memory, performed by a processing unit, including steps of: obtaining a logical address associated with a data read operation; determining whether a group table corresponding to the logical address is queued in a locked queue, or a hot zone of a swap queue; and prohibiting content of the locked queue and the swap queue from being modified when the group table corresponding to the logical address is queued in the locked queue, or the hot zone of the swap queue.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: August 10, 2021
    Assignee: SILICON MOTION, INC.
    Inventors: Kuan-Te Li, Sheng-Hsun Lin, Kuei-Sung Hsu, Jian-Wei Sun
  • Patent number: 11068391
    Abstract: A mapping table updating method executable by a data storage device is provided. The data storage device includes a non-volatile memory and a controller. The mapping table updating method includes steps of: step A: configuring the controller to process a command issued by a host, and determine whether to trigger a partial garbage collection procedure when the command is a write command; when it is determined to trigger the partial garbage collection procedure, then performing step B: copying partial valid data in at least one source block to a destination block according to a segmentation condition; and step C: updating a logical-to-physical address mapping table of the data storage device according to a logical address of the copied partial valid data and a physical address in the destination block where the partial valid data is located, and returning to perform the step A.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: July 20, 2021
    Assignee: Silicon Motion, Inc.
    Inventors: Kuei-Sung Hsu, Jian-Wei Sun, Ting-Heng Chou
  • Patent number: 11030093
    Abstract: A high efficiency garbage collection method, an associated data storage device and a controller thereof are provided. The high efficiency garbage collection method includes: starting and executing a garbage collection procedure; determining whether a Trim command from a host device is received; in response to the Trim command being received, determining whether target data of the Trim command is stored in a source block of the garbage collection procedure; in response to the target data being stored in the source block, determining whether the target data stored in the source block has been copied to a destination block of the garbage collection procedure; and in response to the target data stored in the source block having been copied to the destination block, changing at least one physical address of the target data of the Trim command to a Trim tag in a logical-to-physical address mapping table.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: June 8, 2021
    Assignee: Silicon Motion, Inc.
    Inventors: Ting-Heng Chou, Jian-Wei Sun
  • Publication number: 20210011859
    Abstract: The invention introduces a method for controlling data access to a flash memory, performed by a processing unit, including steps of: obtaining a logical address associated with a data read operation; determining whether a group table corresponding to the logical address is queued in a locked queue, or a hot zone of a swap queue; and prohibiting content of the locked queue and the swap queue from being modified when the group table corresponding to the logical address is queued in the locked queue, or the hot zone of the swap queue.
    Type: Application
    Filed: December 27, 2019
    Publication date: January 14, 2021
    Applicant: Silicon Motion, Inc.
    Inventors: Kuan-Te LI, Sheng-Hsun LIN, Kuei-Sung HSU, Jian-Wei SUN
  • Publication number: 20200356491
    Abstract: A data storage device is provided. The data storage device includes a flash memory, a dynamic random access memory (DRAM), and a memory controller. The flash memory is configured to store a logical-to-physical mapping (L2P) table that is divided into a plurality of group-mapping (G2P) tables. The memory controller includes a first processing core and a second processing core. The first processing core receives a host access command from a host. When a specific G2P table corresponding to a specific logical address in the host access command is not stored in the DRAM, the first processing core determines whether the second processing core has loaded the specific G2P table from the flash memory to the DRAM according to the values in a first column in a first bit map and in a second column of a second bit map.
    Type: Application
    Filed: April 17, 2020
    Publication date: November 12, 2020
    Inventors: Jui-Lin YEN, Sheng-Hsun LIN, Jian-Wei SUN
  • Publication number: 20200310643
    Abstract: The invention introduces a non-transitory computer program product for reading partial data of a page on multiple planes when executed by a processor core includes program code to: provide a scheduling table; put each flash-memory access command of a command queue into a cell of the scheduling table according to physical address information of the flash-memory access command; select two flash-memory access commands or more for a logical unit number (LUN) according to the content of the scheduling table; drive a flash interface to perform a multi-page read lite (MPR-Lite) operation for reading data requested by the selected flash-memory access commands from the LUN; and reply with the read data to a host.
    Type: Application
    Filed: December 30, 2019
    Publication date: October 1, 2020
    Applicant: Silicon Motion, Inc.
    Inventors: Kuan-Te LI, Jian-Wei SUN, Ting-Heng CHOU
  • Patent number: 10776280
    Abstract: A data storage device is provided. The data storage includes: a flash memory, a dynamic random access memory (DRAM), and a memory controller. The flash memory stores a logical-to-physical mapping (L2P) table that is divided into a plurality of group-mapping (G2P) tables, and includes a first logical unit number (LUN) and a second LUN that are respectively controlled by a first chip enable (CE) signal and a second CE signal. The memory controller receives a write command from a host, and forms super page data using logical pages of data in the write command. The memory controller reads one of the group-mapping tables from the first LUN or the second LUN to the DRAM after sequentially enabling the first CE signal and second CE signal to write a first portion and a second portion of the super page data to the first LUN and the second LUN.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: September 15, 2020
    Assignee: SILICON MOTION, INC.
    Inventors: Chen-Ning Yang, Chien-Chung Chung, Jian-Wei Sun
  • Publication number: 20200233610
    Abstract: A data storage device is provided. The data storage device includes a flash memory, a dynamic random access memory (DRAM), and a controller. The flash memory stores a logical-to-physical mapping (L2P) table which is divided into a plurality of group-mapping tables. The DRAM stores a first set of the group-mapping tables. The controller loads a second set of the group mapping tables from the flash memory to the DRAM to replace the first set of the group-mapping tables using a predetermined replacement mechanism, and each group-mapping table of the second set has a corresponding column in an access information table that includes a flag and an access count. In response to the corresponding column of a specific group-mapping table in the second set not being zero, the controller excludes the specific group-mapping table from the predetermined replacement mechanism.
    Type: Application
    Filed: September 27, 2019
    Publication date: July 23, 2020
    Inventors: Jian-Wei SUN, Sheng-Hsun LIN, Jui-Lin YEN, Chien-Hsin KO
  • Publication number: 20200089608
    Abstract: A high efficiency garbage collection method, an associated data storage device and a controller thereof are provided. The high efficiency garbage collection method includes: starting and executing a garbage collection procedure; determining whether a Trim command from a host device is received; in response to the Trim command being received, determining whether target data of the Trim command is stored in a source block of the garbage collection procedure; in response to the target data being stored in the source block, determining whether the target data stored in the source block has been copied to a destination block of the garbage collection procedure; and in response to the target data stored in the source block having been copied to the destination block, changing at least one physical address of the target data of the Trim command to a Trim tag in a logical-to-physical address mapping table.
    Type: Application
    Filed: June 18, 2019
    Publication date: March 19, 2020
    Inventors: Ting-Heng Chou, Jian-Wei Sun
  • Publication number: 20200081832
    Abstract: A mapping table updating method executable by a data storage device is provided. The data storage device includes a non-volatile memory and a controller. The mapping table updating method includes steps of: step A: configuring the controller to process a command issued by a host, and determine whether to trigger a partial garbage collection procedure when the command is a write command; when it is determined to trigger the partial garbage collection procedure, then performing step B: copying partial valid data in at least one source block to a destination block according to a segmentation condition; and step C: updating a logical-to-physical address mapping table of the data storage device according to a logical address of the copied partial valid data and a physical address in the destination block where the partial valid data is located, and returning to perform the step A.
    Type: Application
    Filed: August 16, 2019
    Publication date: March 12, 2020
    Inventors: Kuei-Sung Hsu, Jian-Wei Sun, Ting-Heng Chou
  • Patent number: D722560
    Type: Grant
    Filed: September 12, 2013
    Date of Patent: February 17, 2015
    Assignee: Johnson Electric S.A.
    Inventors: James Ching Sik Lau, Duncan Yiu Lung Wong, Chun Kit Cheung, Jian Wei Sun