Abstract: A multi-chip package structure comprising a first chip, a patterned lamination layer, a plurality of first bumps, a second chip and second bumps is provided. The first chip has a first active surface. The patterned lamination layer is disposed on a portion area of the first active surface. The first chip has a plurality of first bonding pads disposed on the first active surface exposed by the patterned lamination layer and the patterned lamination layer has a plurality of second bonding pads disposed thereon. The second chip has a second active surface and the first bumps are disposed on the second active surface. The second chip is electrically connected to the first bonding pads through the first bumps. The second bumps are disposed on the second bonding pads. Moreover, the multi-chip package structure further comprises a component disposed on the first chip and electrically connects to the first bonding pads.

Abstract: A process for manufacturing transparent semiconductor packages is disclosed. A wafer having an active surface and a back surface is provided. A plurality of first redistribution lines are formed on the active surface of the wafer to connect the bonding pads of the chips. A transparent polymer is formed over the active surface of the wafer to cover the first redistribution lines. A plurality of first grooves are formed corresponding to the scribe lines and in the back surface of the wafer. Preferably, a back coating is then formed over the back surface to fill the first grooves. Next, a plurality of second grooves are formed corresponding to the first grooves and through the back coating such that the first redistribution lines have exposed portions. A plurality of second redistribution lines on the back coating can extend to the exposed portions of the corresponding first redistribution lines for connecting solder balls on the back surface.