Abstract: A lateral double diffusion metal-oxide-semiconductor (LDMOS) transistor is provided. The LDMOS transistor includes a semiconductor substrate having a well region and a drain region in the well region. The LDMOS transistor also includes at least one drifting region in the well region and an annular source region in the drifting region surrounding the drain region. Further, the LDMOS transistor includes at least one annular isolation structure surrounding the drain region in the drifting region. Further, the LDMOS transistor also includes an annular gate dielectric layer on the well region and an annular gate on the annular gate dielectric layer.

Abstract: A lateral double diffusion metal-oxide-semiconductor (LDMOS) transistor is provided. The LDMOS transistor includes a semiconductor substrate having a well region and a drain region in the well region. The LDMOS transistor also includes at least one drifting region in the well region and an annular source region in the drifting region surrounding the drain region. Further, the LDMOS transistor includes at least one annular isolation structure surrounding the drain region in the drifting region. Further, the LDMOS transistor also includes an annular gate dielectric layer on the well region and an annular gate on the annular gate dielectric layer.

Abstract: An EEPROM integrated circuit structure. The structure has a substrate that includes a surface region. Preferably, the surface region is provided within a first cell region. The structure also has a gate dielectric layer of first thickness overlying the surface of the substrate region and a select gate overlying a first portion of the gate dielectric layer. A floating gate is overlying a second portion of the gate dielectric layer and is coupled to the select gate. An insulating layer is overlying the floating gate. A control gate is overlying the insulating layer and is coupled to the floating gate. A tunnel window provided in a stripe configuration is formed within a portion of the gate dielectric layer. The portion of the gate dielectric layer is characterized by a second thickness, which is less than the first thickness.