Abstract: A display panel and a display device are disclosed. The display panel includes signal lines, and the signal lines include a signal main section disposed in a bezel area and a signal connecting section having one end connected to the signal main section and another end extending to a terminal area. The signal main section includes a first side and a second side, and the signal main section corresponding to the first side is adjacent to a display area. The signal connecting section includes a third side and a fourth side, the third side is connected to the first side, and at least a part of the signal connecting section corresponding to the third side is concavo-convex shaped.

Abstract: A pixel arrangement structure provided by the present invention comprises a plurality of pixel groups. Each of the pixel groups comprises a first pixel, a second pixel, a third pixel, and a fourth pixel, wherein the first pixel includes a first sub-pixel and a second sub-pixel, and the second pixel includes the first sub-pixel and one second sub-pixel, two second sub-pixels in the first pixel and the second pixel share one same first sub-pixel, the third pixel and the fourth pixel both comprise a third sub-pixel and one second sub-pixel, two second sub-pixels in the third pixel and the fourth pixel share one same third sub-pixel, and the second sub-pixel is a blue sub-pixel. The invention increases the service lifespan of the blue sub-pixel.

Abstract: An array substrate and a display panel are provided. The array substrate has a plurality of first power lines and a plurality of second power lines connecting with power lines within corresponding fan-out areas, respectively. The first power lines and the second power lines are arranged in parallel to each other and staggered within a display area. At least one of the first power lines within an anti-static area connects with one of the second power lines adjacent to the first power line thereby solving the problem of voltage drop and line defects caused by unilateral driving.

Abstract: A display panel and a manufacturing method thereof, the display panel includes a first sub-pixel strip, a second sub-pixel strip, and a third sub-pixel strip arranged in a row direction or a column direction. The sub-pixels on each sub-pixel strip of the present disclosure have the same color and are arranged in series. The first sub-pixels on the first sub-pixel strip and the second sub-pixels on the second sub-pixel strip are staggered to improve flatness of printing the luminous material and luminous uniformity of OLED devices.

Abstract: The present disclosure provides a preservation method for room temperature logistics of fresh meat, e.g., pork, including the following steps: cutting a slaughtered pig into pieces while the pork is hot, and cooling to 0° C. to 4° C.; cooling again to ?4° C. to ?2° C. so that the meat pieces reach a chilled/slightly-frozen state; sub-packaging the chilled/slightly-frozen meat pieces; putting sub-packaging boxes with fresh meat pieces into an insulation foam box together with ice bags for packaging; and using a room temperature logistics vehicle for transportation and distribution, where, when in an ambient temperature is at least 24° C. (e.g., summer), transportation and distribution time is ?36 h; and when the ambient temperature is less than 24° C. (e.g., spring, autumn, and winter), the transportation and distribution time is ?72 h.

Abstract: A display panel with a high aperture ratio, a manufacturing method thereof, and a display device are provided. The display panel includes effective light emitting regions and invalid light emitting regions. Added opening regions are further defined on the invalid light emitting regions of the display panel. Color filter layers are formed in the added opening regions. Regions where the color filter layers in the added opening regions on the display panel are located on are added effective light emitting regions. An aperture ratio and a pixel density of the display panel can be increased to achieve a purpose of improving display effect of the display panel.

Abstract: A display panel with a high aperture ratio, a manufacturing method thereof, and a display device are provided. The display panel includes effective light emitting regions and invalid light emitting regions. Added opening regions are further defined on the invalid light emitting regions of the display panel. Color filter layers are formed in the added opening regions. Regions where the color filter layers in the added opening regions on the display panel are located on are added effective light emitting regions. An aperture ratio and a pixel density of the display panel can be increased to achieve a purpose of improving display effect of the display panel.

Abstract: A pixel arrangement structure is provided in the present application. The pixel arrangement structure, including: a plurality of matrix units with three rows and six columns arranged in array, wherein the matrix unit with three rows and six columns includes two third-order matrix subunits, and each one of the third-order matrix subunits includes 3×3 sub-pixel units. The sub-pixel units with the same color are arranged in a predetermined slash direction in the pixel arrangement structure. An organic light emitting diode (OLED) display device using the pixel arrangement structure is also provided in the present application.

Abstract: A method for processing a mortise of a small-size superalloy turbine disk using laser shock peening A laser shock peening (LSP) parameter of a laser shock peening (LSP) robot is designed. A spatial data of a motion trajectory of the LSP robot for a laser shock peening area of mortise teeth of the first mortise is found and recorded using a robot simulation system software to generate a trajectory program of the robot for the first mortise. Then a rotation program of an end of an arm of the LSP robot is written according to an included angle between two adjacent mortises to generate a trajectory program of the robot for all mortises of the turbine disk. Finally, the turbine disk is processed by laser shock peening.

Abstract: A robotic laser-guiding device for laser shock peening includes a laser-guiding arm, a reflecting mirror and a manipulator. The laser-guiding arm includes a laser entry tube, a laser-guiding tube, a laser exit tube and a laser shock head sequentially connected. The laser entry tube is rotatably connected to the laser-guiding tube through a joint. The laser-guiding tube is rotatably connected to the laser exit tube through a joint. The laser entry tube is connected to a laser generator. Each joint is provided with the reflecting mirror. The laser emitted by the laser generator passes through the laser entry tube, one reflecting mirror, the laser-guiding tube, another reflecting mirror, the laser exit tube and the laser shock head to irradiate a part, so as to perform the laser shock peening.

Abstract: A liquid crystal display panel and a testing method thereof are provided. A circuit is shared for a box test and an array test, and a plurality of test lines and a plurality of test pads are not needed to be disposed in the liquid crystal display panel separately for the box test and the array test, that is, areas for disposing the plurality of test lines and the plurality of test pads are not needed to be reserved for the box test and the array test, which can increase a cuttable size of the liquid crystal display panel and increase a number of extractions from the liquid crystal display panel.

Abstract: A display panel and a manufacturing method thereof, the display panel includes a first sub-pixel strip, a second sub-pixel strip, and a third sub-pixel strip arranged in a row direction or a column direction. The sub-pixels on each sub-pixel strip of the present disclosure have the same color and are arranged in series. The first sub-pixels on the first sub-pixel strip and the second sub-pixels on the second sub-pixel strip are staggered to improve flatness of printing the luminous material and luminous uniformity of OLED devices.

Abstract: A pixel circuit and a display device are provided. The pixel circuit includes three transistors, a storage capacitor, a light emitting device, a data line, a scan line, and a detection signal line. A control electrode of a third transistor in a nth row is connected to a scan line in a n+1th row. The scan lines in adjacent rows have at least half of pulses being the same. A second transistor and the third transistor are separately controlled to improve detection accuracy of a threshold voltage and improve compensation accuracy of the pixel circuit.

Abstract: An array substrate and a display panel are provided. The array substrate has a plurality of first power lines and a plurality of second power lines connecting with power lines within corresponding fan-out areas, respectively. The first power lines and the second power lines are arranged in parallel to each other and staggered within a display area. At least one of the first power lines within an anti-static area connects with one of the second power lines adjacent to the first power line thereby solving the problem of voltage drop and line defects caused by unilateral driving.

Abstract: An integrated circuit including a trench in the substrate with a high quality trench oxide grown on the sidewalls and the bottom of the trench where the ratio of the thickness of the high quality trench oxide formed on the sidewalls to the thickness formed on the bottom is less than 1.2. An integrated circuit including a trench with high quality oxide is formed by first growing a sacrificial oxide in dilute oxygen at a temperature in the range of 1050° C. to 1250° C., stripping the sacrificial oxide, growing high quality oxide in dilute oxygen plus trans 1,2 dichloroethylene at a temperature in the range of 1050° C. to 1250° C., and annealing the high quality oxide in an inert ambient at a temperature in the range of 1050° C. to 1250° C.

Abstract: An integrated circuit including a trench in the substrate with a high quality trench oxide grown on the sidewalls and the bottom of the trench where the ratio of the thickness of the high quality trench oxide formed on the sidewalls to the thickness formed on the bottom is less than 1.2. An integrated circuit including a trench with high quality oxide is formed by first growing a sacrificial oxide in dilute oxygen at a temperature in the range of 1050° C. to 1250° C., stripping the sacrificial oxide, growing high quality oxide in dilute oxygen plus trans 1,2 dichloroethylene at a temperature in the range of 1050° C. to 1250° C., and annealing the high quality oxide in an inert ambient at a temperature in the range of 1050° C. to 1250° C.

Abstract: An integrated circuit including a trench in the substrate with a high quality trench oxide grown on the sidewalls and the bottom of the trench where the ratio of the thickness of the high quality trench oxide formed on the sidewalls to the thickness formed on the bottom is less than 1.2. An integrated circuit including a trench with high quality oxide is formed by first growing a sacrificial oxide in dilute oxygen at a temperature in the range of 1050° C. to 1250° C., stripping the sacrificial oxide, growing high quality oxide in dilute oxygen plus trans 1,2 dichloroethylene at a temperature in the range of 1050° C. to 1250° C., and annealing the high quality oxide in an inert ambient at a temperature in the range of 1050° C. to 1250° C.

Abstract: An integrated circuit including a trench in the substrate with a high quality trench oxide grown on the sidewalls and the bottom of the trench where the ratio of the thickness of the high quality trench oxide formed on the sidewalls to the thickness formed on the bottom is less than 1.2. An integrated circuit including a trench with high quality oxide is formed by first growing a sacrificial oxide in dilute oxygen at a temperature in the range of 1050° C. to 1250° C., stripping the sacrificial oxide, growing high quality oxide in dilute oxygen plus trans 1,2 dichloroethylene at a temperature in the range of 1050° C. to 1250° C., and annealing the high quality oxide in an inert ambient at a temperature in the range of 1050° C. to 1250° C.

Abstract: An integrated circuit including a trench in the substrate with a high quality trench oxide grown on the sidewalls and the bottom of the trench where the ratio of the thickness of the high quality trench oxide formed on the sidewalls to the thickness formed on the bottom is less than 1.2. An integrated circuit including a trench with high quality oxide is formed by first growing a sacrificial oxide in dilute oxygen at a temperature in the range of 1050° C. to 1250° C., stripping the sacrificial oxide, growing high quality oxide in dilute oxygen plus trans 1,2 dichloroethylene at a temperature in the range of 1050° C. to 1250° C., and annealing the high quality oxide in an inert ambient at a temperature in the range of 1050° C. to 1250° C.

Abstract: A method for forming bond pads on a semiconductor die includes forming a dielectric stack including a bottom and top dielectric layer having a contact hole therethrough over a bond pad. An outer edge of the bottom dielectric layer within the contact hole extends beyond an outer edge of the top dielectric layer to define a bond pad edge. A second metal layer on a first metal layer is deposited. A first photoresist layer is formed exclusively within the contact hole. The second metal layer is wet etched to recess the second metal layer from sidewalls of the bottom dielectric layer in the contact hole. A second photoresist layer is formed exclusively within the contact hole. The first metal layer is wet etched to recess the first metal layer from the top dielectric layer. The first metal layer extends over the bond pad edge onto the bottom dielectric layer.