Patents by Inventor Jian-Yi Li
Jian-Yi Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11945302Abstract: A low-floor electric axle assembly including: an axle housing, two hub motors, two planetary gear reducers, two hubs, a brake system, two C-shaped beams, and a suspension system. Mechanical mounting of the suspension system is compatible with a conventional axle. The axle housing has a left and right symmetrical dumbbell-shaped structure configured to bear a weight of a vehicle. The hub motors are inner rotor type motors and are separately arranged at two ends of the axle housing left and right symmetrically. The hub motors are arranged coaxially with two wheels respectively. Two hub motor rotors are connected to the planetary gear reducers respectively. Each of the planetary gear reducers is a single-stage planetary gear reducer. A sun gear of each of the planetary gear reducers receives power outputted by each of the hub motor. Two planetary gear reducer housings are power output ends connected to two rims respectively.Type: GrantFiled: November 13, 2020Date of Patent: April 2, 2024Assignee: TSINGHUA UNIVERSITYInventors: Jian-Qiu Li, Jia-Yi Hu, Liang-Fei Xu, Bing-Kun Cai, Hang Li
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Patent number: 10878167Abstract: A method including decomposing a conflict graph based on a number of masked to be used to manufacture a semiconductor device. The method further includes determining whether the decomposed conflict graph is a simplified graph based on a comparison between the decomposed conflict graph and a stored conflict graph. The method further includes determining whether the decomposed conflict graph is colorable based on a number of masks used to pattern the layer of the semiconductor device. The method further includes indicating that the conflict graph is colorable in response to a determination that the decomposed conflict graph is colorable.Type: GrantFiled: December 11, 2019Date of Patent: December 29, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chung-Yun Cheng, Chin-Chang Hsu, Hsien-Hsin Sean Lee, Jian-Yi Li, Li-Sheng Ke, Wen-Ju Yang
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Publication number: 20200117848Abstract: A method including decomposing a conflict graph based on a number of masked to be used to manufacture a semiconductor device. The method further includes determining whether the decomposed conflict graph is a simplified graph based on a comparison between the decomposed conflict graph and a stored conflict graph. The method further includes determining whether the decomposed conflict graph is colorable based on a number of masks used to pattern the layer of the semiconductor device. The method further includes indicating that the conflict graph is colorable in response to a determination that the decomposed conflict graph is colorable.Type: ApplicationFiled: December 11, 2019Publication date: April 16, 2020Inventors: Chung-Yun CHENG, Chin-Chang HSU, Hsien-Hsin Sean LEE, Jian-Yi LI, Li-Sheng KE, Wen-Ju YANG
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Patent number: 10515185Abstract: A method of determining colorability of a layer of a semiconductor device includes iteratively decomposing a conflict graph to remove all nodes having fewer links than a threshold number of links. The method further includes determining whether the decomposed conflict graph is a simplified graph based on a comparison between the decomposed conflict graph and a stored conflict graph. The method further includes determining whether the decomposed conflict graph is colorable based on a number of masks used to pattern the layer of the semiconductor device. The method further includes flagging violations in response to a determination that the decomposed conflict graph is not colorable.Type: GrantFiled: February 11, 2019Date of Patent: December 24, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chung-Yun Cheng, Chin-Chang Hsu, Hsien-Hsin Sean Lee, Jian-Yi Li, Li-Sheng Ke, Wen-Ju Yang
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Publication number: 20190171789Abstract: A method of determining colorability of a layer of a semiconductor device includes iteratively decomposing a conflict graph to remove all nodes having fewer links than a threshold number of links. The method further includes determining whether the decomposed conflict graph is a simplified graph based on a comparison between the decomposed conflict graph and a stored conflict graph. The method further includes determining whether the decomposed conflict graph is colorable based on a number of masks used to pattern the layer of the semiconductor device. The method further includes flagging violations in response to a determination that the decomposed conflict graph is not colorable.Type: ApplicationFiled: February 11, 2019Publication date: June 6, 2019Inventors: Chung-Yun CHENG, Chin-Chang HSU, Hsien-Hsin Sean LEE, Jian-Yi LI, Li-Sheng KE, Wen-Ju YANG
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Patent number: 10204205Abstract: A method of determining colorability of a layer of a semiconductor device includes iteratively decomposing a conflict graph to remove all nodes having fewer links than a threshold number of links. The method further includes determining whether the decomposed conflict graph is a simplified graph. The method further includes partitioning, using a specific purpose processing device, the decomposed conflict graph if the decomposed conflict graph is not a simplified graph. The method further includes determining whether the decomposed conflict graph is colorable based on a number of masks used to pattern the layer of the semiconductor device if the decomposed conflict graph is a simplified graph. The method further includes flagging violations if the decomposed conflict graph is not colorable.Type: GrantFiled: January 7, 2016Date of Patent: February 12, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chung-Yun Cheng, Chin-Chang Hsu, Hsien-Hsin Sean Lee, Jian-Yi Li, Li-Sheng Ke, Wen-Ju Yang
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Publication number: 20170199957Abstract: A method of determining colorability of a layer of a semiconductor device includes iteratively decomposing a conflict graph to remove all nodes having fewer links than a threshold number of links. The method further includes determining whether the decomposed conflict graph is a simplified graph. The method further includes partitioning, using a specific purpose processing device, the decomposed conflict graph if the decomposed conflict graph is not a simplified graph. The method further includes determining whether the decomposed conflict graph is colorable based on a number of masks used to pattern the layer of the semiconductor device if the decomposed conflict graph is a simplified graph. The method further includes flagging violations if the decomposed conflict graph is not colorable.Type: ApplicationFiled: January 7, 2016Publication date: July 13, 2017Inventors: Chung-Yun CHENG, Chin-Chang HSU, Hsien-Hsin Sean LEE, Jian-Yi LI, Li-Sheng KE, Wen-Ju YANG
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Patent number: 9111065Abstract: A method of inserting dummy metal and dummy via in an integrated circuit design includes inserting, by a computer, dummy metals using a place and route tool, wherein the place and route tool has timing-awareness to improve a timing performance of the integrated circuit design, and the dummy metals have a length less than or equal to a predetermined maximum length. The method further includes inserting, by the computer, dummy vias using a design-rule-checking utility separately from the inserting of the dummy metals.Type: GrantFiled: January 16, 2014Date of Patent: August 18, 2015Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hung-Yi Liu, Chung-Hsing Wang, Chih-Chieh Chen, Jian-Yi Li
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Patent number: 8943454Abstract: In some embodiments, in a method for considering in-phase grouping for a voltage-dependent design rule, for a first net and a second net in a schematic, first data for obtaining the differences between first voltage values of the first and second nets, and between second voltage values of the first and second nets is provided. For each of the first and second nets, the first voltage value is larger than the second voltage value. A layout for the schematic is generated. In the layout, a relationship of a first shape and a second shape associated with the first and the second nets, respectively, is defined using the first data.Type: GrantFiled: November 5, 2013Date of Patent: January 27, 2015Assignee: Taiwan Semiconductor Manufacturing Company Ltd.Inventors: Chih Chi Hsiao, Jill Liu, Wei-Yi Hu, Jui-Feng Kuan, Yu-Ren Chen, Kuo-Ji Chen, Jian-Yi Li, Wen-Ju Yang
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Publication number: 20140137060Abstract: A method of inserting dummy metal and dummy via in an integrated circuit design includes inserting, by a computer, dummy metals using a place and route tool, wherein the place and route tool has timing-awareness to improve a timing performance of the integrated circuit design, and the dummy metals have a length less than or equal to a predetermined maximum length. The method further includes inserting, by the computer, dummy vias using a design-rule-checking utility separately from the inserting of the dummy metals.Type: ApplicationFiled: January 16, 2014Publication date: May 15, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hung-Yi LIU, Chung-Hsin WANG, Chih-Chieh CHEN, Jian-Yi LI
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Patent number: 8661395Abstract: A method of inserting dummy metal and dummy via in an integrated circuit design. The method includes inserting, by a computer, dummy metals using a place and route tool, wherein the place and route tool has timing-awareness to improve a timing performance of the integrated circuit design. The method further includes inserting, by the computer, dummy vias using a design-rule-checking utility separately from the inserting of the dummy metals, wherein at least one of the dummy vias has a different size than at least another of the dummy vias.Type: GrantFiled: October 5, 2012Date of Patent: February 25, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Yi Liu, Chung-Hsing Wang, Chih-Chieh Chen, Jian-Yi Li
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Patent number: 8350330Abstract: A method of forming an integrated circuit structure on a chip includes extracting an active pattern including a diffusion region; enlarging the active pattern to form a dummy-forbidden region having a first edge and a second edge perpendicular to each other; and adding stress-blocking dummy diffusion regions throughout the chip, which includes adding a first stress-blocking dummy diffusion region adjacent and substantially parallel to the first edge of the dummy-forbidden region; and adding a second stress-blocking dummy diffusion region adjacent and substantially parallel to the second edge of the dummy-forbidden region. The method further includes, after the step of adding the stress-blocking dummy diffusion regions throughout the chip, adding general dummy diffusion regions into remaining spacings of the chip. A structure includes a target diffusion region including a first edge with a first length and a second edge with a second edge perpendicular to the first length.Type: GrantFiled: May 2, 2011Date of Patent: January 8, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Lee-Chung Lu, Chien-Chih Kuo, Jian-Yi Li, Sheng-Jier Yang
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Patent number: 8307321Abstract: A method for dummy metal and dummy via insertion is provided. In one embodiment, dummy metals are inserted using a place and route tool, where the place and route tool has timing-awareness. Then, dummy vias arrays are inserted inside an overlap area of dummy metals using a design-rule-checking utility. Fine-grained dummy vias arrays are inserted in available space far away from main patterns. The dummy-patterns resulting from the inserted dummy vias are compressed using the design-rule-checking utility to reduce the size of a graphic data system file generated from the integrated circuit design. The dummy vias can be inserted with relaxed via spacing rules. The dummy metals are inserted with a constant line-end spacing between them for better process control and the maximum length of the dummy metal can be limited for smaller coupling effects. The dummy vias can have various sizes and a square or rectangular shape.Type: GrantFiled: March 22, 2010Date of Patent: November 6, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Yi Liu, Chung-Hsing Wang, Chih-Chieh Chen, Jian-Yi Li
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Publication number: 20110204449Abstract: A method of forming an integrated circuit structure on a chip includes extracting an active pattern including a diffusion region; enlarging the active pattern to form a dummy-forbidden region having a first edge and a second edge perpendicular to each other; and adding stress-blocking dummy diffusion regions throughout the chip, which includes adding a first stress-blocking dummy diffusion region adjacent and substantially parallel to the first edge of the dummy-forbidden region; and adding a second stress-blocking dummy diffusion region adjacent and substantially parallel to the second edge of the dummy-forbidden region. The method further includes, after the step of adding the stress-blocking dummy diffusion regions throughout the chip, adding general dummy diffusion regions into remaining spacings of the chip.Type: ApplicationFiled: May 2, 2011Publication date: August 25, 2011Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Lee-Chung Lu, Chien-Chih Kuo, Jian-Yi Li, Sheng-Jier Yang
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Patent number: 7958465Abstract: A method of forming an integrated circuit structure on a chip includes extracting an active pattern including a diffusion region; enlarging the active pattern to form a dummy-forbidden region having a first edge and a second edge perpendicular to each other; and adding stress-blocking dummy diffusion regions throughout the chip, which includes adding a first stress-blocking dummy diffusion region adjacent and substantially parallel to the first edge of the dummy-forbidden region; and adding a second stress-blocking dummy diffusion region adjacent and substantially parallel to the second edge of the dummy-forbidden region. The method further includes, after the step of adding the stress-blocking dummy diffusion regions throughout the chip, adding general dummy diffusion regions into remaining spacings of the chip.Type: GrantFiled: September 16, 2008Date of Patent: June 7, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Lee-Chung Lu, Chien-Chih Kuo, Jian-Yi Li, Sheng-Jier Yang
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Publication number: 20100242008Abstract: A method for dummy metal and dummy via insertion is provided. In one embodiment, dummy metals are inserted using a place and route tool, where the place and route tool has timing-awareness. Then, dummy vias arrays are inserted inside an overlap area of dummy metals using a design-rule-checking utility. Fine-grained dummy vias arrays are inserted in available space far away from main patterns. The dummy-patterns resulting from the inserted dummy vias are compressed using the design-rule-checking utility to reduce the size of a graphic data system file generated from the integrated circuit design. The dummy vias can be inserted with relaxed via spacing rules. The dummy metals are inserted with a constant line-end spacing between them for better process control and the maximum length of the dummy metal can be limited for smaller coupling effects. The dummy vias can have various sizes and a square or rectangular shape.Type: ApplicationFiled: March 22, 2010Publication date: September 23, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hung-Yi LIU, Chung-Hsing WANG, Chih-Chieh CHEN, Jian-Yi LI
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Publication number: 20090282374Abstract: A method of forming an integrated circuit structure on a chip includes extracting an active pattern including a diffusion region; enlarging the active pattern to form a dummy-forbidden region having a first edge and a second edge perpendicular to each other; and adding stress-blocking dummy diffusion regions throughout the chip, which includes adding a first stress-blocking dummy diffusion region adjacent and substantially parallel to the first edge of the dummy-forbidden region; and adding a second stress-blocking dummy diffusion region adjacent and substantially parallel to the second edge of the dummy-forbidden region. The method further includes, after the step of adding the stress-blocking dummy diffusion regions throughout the chip, adding general dummy diffusion regions into remaining spacings of the chip.Type: ApplicationFiled: September 16, 2008Publication date: November 12, 2009Inventors: Lee-Chung Lu, Chien-Chih Kuo, Jian-Yi Li, Sheng-Jier Yang