Patents by Inventor Jian-Yu Ding
Jian-Yu Ding has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9685966Abstract: A fractional dividing module includes an output clock generating circuit, for receiving an input clock signal and generating an output clock signal according to a first control signal, comprising a first delay unit, for delaying the input clock signal to generate a delayed input clock signal; and a selecting unit, for selecting one of the input clock signal and the delayed input clock signal to generate the output clock signal according to the first control signal; and a control circuit, for dividing the output clock signal to generate the first control signal according to a dividing control signal, wherein the dividing control is adjusted to control a frequency ratio between the output clock signal and the input clock signal.Type: GrantFiled: October 26, 2015Date of Patent: June 20, 2017Assignee: MEDIATEK INC.Inventors: Pang-Ning Chen, Yu-Li Hsueh, Jian-Yu Ding
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Publication number: 20160156364Abstract: A fractional dividing module includes an output clock generating circuit, for receiving an input clock signal and generating an output clock signal according to a first control signal, comprising a first delay unit, for delaying the input clock signal to generate a delayed input clock signal; and a selecting unit, for selecting one of the input clock signal and the delayed input clock signal to generate the output clock signal according to the first control signal; and a control circuit, for dividing the output clock signal to generate the first control signal according to a dividing control signal, wherein the dividing control is adjusted to control a frequency ratio between the output clock signal and the input clock signal.Type: ApplicationFiled: October 26, 2015Publication date: June 2, 2016Inventors: Pang-Ning Chen, Yu-Li Hsueh, Jian-Yu Ding
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Patent number: 9071255Abstract: A phase locked loop and an associated alignment method are provided. A disclosed phase locked loop receives a reference signal to provide a feedback signal. The phase locked loop is first opened. When the phase locked loop is open, a frequency range of an oscillating signal from a voltage-controlled oscillator is substantially selected. The feedback signal is provided according to the oscillation signal. After the frequency range is selected, the phase locked loop is kept open and the phases of the reference signal and the feedback signal are substantially aligned. The phase locked loop is then closed after the reference signal and the feedback signal are aligned.Type: GrantFiled: September 11, 2012Date of Patent: June 30, 2015Assignee: MSTAR SEMICONDUCTOR, INC.Inventors: Cheng-Chieh Lin, Jian-Yu Ding, Yao-Chi Wang
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Patent number: 9007132Abstract: An oscillation signal generator includes a quadrature voltage-controlled oscillator (QVCO), a phase corrector and a frequency adjusting circuit. The QVCO provides multiple oscillation signals having difference phases. The phase corrector selects one of the oscillation signals as a first oscillation signal and outputs the first oscillation signal from a first output terminal, and selects one of the oscillation signals as a second oscillation signal and outputs the second oscillation signal from a second output terminal. A phase difference between the first and second oscillation signals satisfies a predetermined relationship. The frequency adjusting circuit is coupled to the phase corrector, and generates a quadrature signal and an in-phase signal according to the oscillation signals. The frequency of the oscillation signals is a non-integral multiple of the frequencies of the quadrature and in-phase signals.Type: GrantFiled: April 23, 2013Date of Patent: April 14, 2015Assignee: MStar Semiconductor, Inc.Inventor: Jian-Yu Ding
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Patent number: 8890585Abstract: A frequency multiplier and associated method are provided, wherein the frequency multiplier includes a waveform generator and a slicer. The waveform generator generates a waveform in response to an input signal, and the slicer induces transitions in an output signal whenever the waveform crosses each of a plurality of reference levels, such that a frequency of the output signal is a multiple of a frequency of the input signal.Type: GrantFiled: November 13, 2012Date of Patent: November 18, 2014Assignee: MStar Semiconductor, Inc.Inventors: Jian-Yu Ding, Shih-Chieh Yen, Ming-Yu Hsieh, Yao-Chi Wang
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Publication number: 20140132313Abstract: A frequency multiplier and associated method are provided, wherein the frequency multiplier includes a waveform generator and a slicer. The waveform generator generates a waveform in response to an input signal, and the slicer induces transitions in an output signal whenever the waveform crosses each of a plurality of reference levels, such that a frequency of the output signal is a multiple of a frequency of the input signal.Type: ApplicationFiled: November 13, 2012Publication date: May 15, 2014Applicant: MSTAR SEMICONDUCTOR, INC.Inventors: Jian-Yu Ding, Shih-Chieh Yen, Ming-Yu Hsieh, Yao-Chi Wang
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Patent number: 8599997Abstract: A multiple-modulus divider and an associated control method are provided. The multiple-modulus divider includes a divisor loader, a multiple-modulus dividing circuit and a modulus controller. The divisor loader downloads a divisor when a download signal indicates a start of a division period. The multiple-modulus circuit includes a plurality of cascaded divisors, and provides an output frequency according to an input frequency and the divisor. The dividers respectively output a plurality of modulus output signals, and each is operable under either a close-loop state or an open-loop state. The modulus controller selects and controls one of the dividers according to the divisor, and ensures the selected divider is maintained at the open-loop state when the division period ends. The download signal corresponds to one of the modulus output signals.Type: GrantFiled: July 24, 2012Date of Patent: December 3, 2013Assignee: MStar Semiconductor, Inc.Inventors: Yen-Tso Chen, Jian-Yu Ding
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Publication number: 20130278344Abstract: An oscillation signal generator includes a quadrature voltage-controlled oscillator (QVCO), a phase corrector and a frequency adjusting circuit. The QVCO provides multiple oscillation signals having difference phases. The phase corrector selects one of the oscillation signals as a first oscillation signal and outputs the first oscillation signal from a first output terminal, and selects one of the oscillation signals as a second oscillation signal and outputs the second oscillation signal from a second output terminal. A phase difference between the first and second oscillation signals satisfies a predetermined relationship. The frequency adjusting circuit is coupled to the phase corrector, and generates a quadrature signal and an in-phase signal according to the oscillation signals. The frequency of the oscillation signals is a non-integral multiple of the frequencies of the quadrature and in-phase signals.Type: ApplicationFiled: April 23, 2013Publication date: October 24, 2013Applicant: MStar Semiconductor, Inc.Inventor: Jian-Yu Ding
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Publication number: 20130070881Abstract: A phase locked loop and an associated alignment method are provided. A disclosed phase locked loop receives a reference signal to provide a feedback signal. The phase locked loop is first opened. When the phase locked loop is open, a frequency range of an oscillating signal from a voltage-controlled oscillator is substantially selected. The feedback signal is provided according to the oscillation signal. After the frequency range is selected, the phase locked loop is kept open and the phases of the reference signal and the feedback signal are substantially aligned. The phase locked loop is then closed after the reference signal and the feedback signal are aligned.Type: ApplicationFiled: September 11, 2012Publication date: March 21, 2013Applicant: MStar Semiconductor, Inc.Inventors: Cheng-Chieh Lin, Jian-Yu Ding, Yao-Chi Wang
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Publication number: 20130027111Abstract: A multiple-modulus divider and an associated control method are provided. The multiple-modulus divider includes a divisor loader, a multiple-modulus dividing circuit and a modulus controller. The divisor loader downloads a divisor when a download signal indicates a start of a division period. The multiple-modulus circuit includes a plurality of cascaded divisors, and provides an output frequency according to an input frequency and the divisor. The dividers respectively output a plurality of modulus output signals, and each is operable under either a close-loop state or an open-loop state. The modulus controller selects and controls one of the dividers according to the divisor, and ensures the selected divider is maintained at the open-loop state when the division period ends. The download signal corresponds to one of the modulus output signals.Type: ApplicationFiled: July 24, 2012Publication date: January 31, 2013Applicant: MStar Semiconductor, Inc.Inventors: YEN-TSO CHEN, Jian-Yu Ding
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Patent number: 7760844Abstract: A multi-modulus divider and a method for performing frequency dividing by utilizing a multi-modulus divider are disclosed. The multi-modulus divider comprises a multi-modulus dividing circuit, a pulse generating circuit, and a modulus signal generating circuit. The multi-modulus dividing circuit comprises several serially connected divider cells, of which a predetermined one may be bypassed. The multi-modulus dividing circuit generates an output frequency according to an input frequency and a divisor. A range of the divisor comprises a plurality of numerical intervals. The pulse generating circuit generates a pulse signal. The modulus signal generating circuit generates a determination result by determining which numerical interval the divisor belongs to, and inputs, according to the determination result, the pulse signal into the predetermined divider cell to be one of references which the predetermined divider cell refers to when outputting a modulus signal.Type: GrantFiled: February 2, 2009Date of Patent: July 20, 2010Assignee: MStar Semiconductor, Inc.Inventors: Jian-Yu Ding, Shen-Ching Sun, Yao-Chi Wang, Chao-Tung Yang, Fucheng Wang, Shuo-Yuan Hsiao
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Publication number: 20100141347Abstract: A band selecting method applied to a voltage controlled oscillator (VCO) of a phase locked loop (PLL) and an associated method is provided. The band selecting method generates an open-loop control voltage according to a temperature signal; inputting the open-loop control voltage into the VCO; switching sequentially between a plurality of frequency bands of the VCO and generating a plurality of voltage controlled signals for the frequency bands; selecting a preferred voltage controlled signal and its corresponding frequency band as an operating band for the PLL.Type: ApplicationFiled: June 16, 2009Publication date: June 10, 2010Applicant: MSTAR SEMICONDUCTOR, INC.Inventors: SHUO YUAN HSIAO, YAO-CHI WANG, SHEN-CHING SUN, JIAN-YU DING
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Publication number: 20090213980Abstract: A multi-modulus divider and a method for performing frequency dividing by utilizing a multi-modulus divider are disclosed. The multi-modulus divider comprises a multi-modulus dividing circuit, a pulse generating circuit, and a modulus signal generating circuit. The multi-modulus dividing circuit comprises several serially connected divider cells, of which a predetermined one may be bypassed. The multi-modulus dividing circuit generates an output frequency according to an input frequency and a divisor. A range of the divisor comprises a plurality of numerical intervals. The pulse generating circuit generates a pulse signal. The modulus signal generating circuit generates a determination result by determining which numerical interval the divisor belongs to, and inputs, according to the determination result, the pulse signal into the predetermined divider cell to be one of references which the predetermined divider cell refers to when outputting a modulus signal.Type: ApplicationFiled: February 2, 2009Publication date: August 27, 2009Inventors: Jian-Yu Ding, Shen-Ching Sun, Yao-Chi Wang, Chao-Tung Yang, Fucheng Wang, Shuo-Yuan Hsiao