Abstract: A sensing amplifier circuit includes first and second P-type transistors and first and second N-type transistors. The first P-type transistor includes a gate coupled to an input node, a source and a bulk coupled to a first node, and a drain coupled to an output node. The second P-type transistor includes a gate coupled to an inverted reading-triggered signal, a source coupled to a voltage source, and a drain coupled to the first node. The first N-type transistor includes a gate coupled to the input node, a drain coupled to the output node, and a source coupled to ground. The second N-type transistor includes a gate receiving the inverted reading-triggered signal, a drain coupled to the output node, and a source coupled to the ground. The first P-type transistor includes an N-type well region that is electrically connected to the source and bulk of the first P-type transistor.

Abstract: A test circuit testing a storage circuit and including a controller, a pattern-generator circuit, a comparing circuit, and a first register is provided. The storage circuit includes a storage block. The controller is configured to generate a plurality of internal test signals. The pattern-generator circuit generates and provides test data to the storage circuit according to the internal test signal. The storage circuit writes the test data into the storage block and reads the storage block to generate read data. The comparing circuit compares the test data and the read data to generate a test result. The first register stores the test result. The controller determines whether the storage circuit is working normally according to the test result stored in the first register.

Abstract: An access method for a memory device is provided. The access method includes receiving external data; reading a plurality of first memory cells of the memory device according to a write address to obtain first original data; comparing the external data and the first original data to determine whether the number of specific cells among the first memory cells is higher than a predetermined value, wherein the value of each of the specific cells would be changed from a first value to a second value in response to the external data being written into the first memory cells; and reversing the external data to generate reversed data and writing the reversed data into the first memory cells to replace the first original data in response to the number of specific cells being higher than the predetermined value.

Abstract: A test circuit testing a storage circuit and including a controller, a pattern-generator circuit, a comparing circuit, and a first register is provided. The controller is configured to generate a plurality of internal test signals. The pattern-generator circuit writes test data into the storage block of the storage circuit according to the internal test signal and reads the storage block to generate read data. The comparing circuit compares the test data and the read data to generate a test result. The first register stores the test result. The controller determines whether the storage circuit is working normally according to the test result stored in the first register.