Abstract: Aspects of the disclosure provide for a circuit including a binary-weighted DAC, a first transistor, a second transistor, a switch, a first current mirror, a second current mirror. The binary-weighted DAC is coupled between a first node and a second node and configured to receive a plurality of bits of a digital control signal. The first transistor has a source coupled to the first node, a drain coupled to a third node, and a gate coupled to a fourth node. The second transistor has a source coupled to the first node, a drain coupled to the third node, and a gate. The switch is coupled between the gate of the second transistor and the fourth node and configured to receive a partition control signal. The first current mirror is coupled to the third node and the second node. The second current mirror is coupled to the first current mirror.

Abstract: Aspects of the disclosure provide for a circuit including a binary-weighted DAC, a first transistor, a second transistor, a switch, a first current mirror, a second current mirror. The binary-weighted DAC is coupled between a first node and a second node and configured to receive a plurality of bits of a digital control signal. The first transistor has a source coupled to the first node, a drain coupled to a third node, and a gate coupled to a fourth node. The second transistor has a source coupled to the first node, a drain coupled to the third node, and a gate. The switch is coupled between the gate of the second transistor and the fourth node and configured to receive a partition control signal. The first current mirror is coupled to the third node and the second node. The second current mirror is coupled to the first current mirror.

Abstract: Aspects of the disclosure provide for a circuit including a binary-weighted DAC, a first transistor, a second transistor, a switch, a first current mirror, a second current mirror. The binary-weighted DAC is coupled between a first node and a second node and configured to receive a plurality of bits of a digital control signal. The first transistor has a source coupled to the first node, a drain coupled to a third node, and a gate coupled to a fourth node. The second transistor has a source coupled to the first node, a drain coupled to the third node, and a gate. The switch is coupled between the gate of the second transistor and the fourth node and configured to receive a partition control signal. The first current mirror is coupled to the third node and the second node. The second current mirror is coupled to the first current mirror.

Abstract: Aspects of the disclosure provide for a circuit including a binary-weighted DAC, a first transistor, a second transistor, a switch, a first current mirror, a second current mirror. The binary-weighted DAC is coupled between a first node and a second node and configured to receive a plurality of bits of a digital control signal. The first transistor has a source coupled to the first node, a drain coupled to a third node, and a gate coupled to a fourth node. The second transistor has a source coupled to the first node, a drain coupled to the third node, and a gate. The switch is coupled between the gate of the second transistor and the fourth node and configured to receive a partition control signal. The first current mirror is coupled to the third node and the second node. The second current mirror is coupled to the first current mirror.