Patents by Inventor Jianan Yang

Jianan Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9899069
    Abstract: Apparatus and methods for operating a read-only memory (ROM) are disclosed. The method for operating the ROM includes sensing a dummy bit line with a dummy sense amplifier coupled to the dummy bit line to generate a keeper adjust signal. Based on the keeper adjust signal, a keeper strength of a keeper circuit coupled to a sense amplifier circuit is adjusted. The sense amplifier circuit is capable of sensing data stored in the ROM.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: February 20, 2018
    Assignee: NXP USA, INC.
    Inventor: Jianan Yang
  • Publication number: 20180033472
    Abstract: Apparatus and methods for operating a read-only memory (ROM) are disclosed. The method for operating the ROM includes sensing a dummy bit line with a dummy sense amplifier coupled to the dummy bit line to generate a keeper adjust signal. Based on the keeper adjust signal, a keeper strength of a keeper circuit coupled to a sense amplifier circuit is adjusted. The sense amplifier circuit is capable of sensing data stored in the ROM.
    Type: Application
    Filed: July 29, 2016
    Publication date: February 1, 2018
    Inventor: JIANAN YANG
  • Patent number: 9691495
    Abstract: A memory array with RAM and embedded ROM including multiple RAM cells, a ROM cell, and a ROM enable circuit. Each RAM cell has a RAM cell structure with a first and second power terminals and configured to operate as a RAM cell when the memory array is in a RAM mode. The ROM cell has the same RAM cell structure in which at least one transistor is modified to cause the ROM cell to have a predetermined logic state. The ROM enable circuit enables bit lines of the ROM cell to control supply voltages provided to the power terminals of the RAM cells so that they settle to predetermined logic states in a ROM mode. The modified transistor has a pseudo transistor structure having a modified substrate that operates as a resistance, such as a doping region in the substrate having the same polarity type as the substrate.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: June 27, 2017
    Assignee: NXP USA, INC.
    Inventors: Jianan Yang, Scott I. Remington, Shayan Zhang
  • Publication number: 20160172052
    Abstract: A read only memory (ROM) having a first row of ROM cells, a first conductive line along the first row of ROM cells, and a second conductive line along the first row of ROM cells. The ROM cells of the first row of ROM cells are selectively coupled during programming to the first conductive line and the second conductive line so that in a first mode of the ROM the first row of ROM cells provide a first combination of logic highs and logic lows and in a second mode of the memory the first row of ROM cells provide a second combination of logic highs and lows independent of the first combination of logic highs and logic lows.
    Type: Application
    Filed: December 10, 2014
    Publication date: June 16, 2016
    Inventors: JIANAN YANG, BRAD J. GARNI, SHAYAN ZHANG
  • Patent number: 9317087
    Abstract: In accordance with at least one embodiment, column level power control granularity is provided to control a low power state of a memory using a drowsy column control bit to control the low power state at an individual column level to protect the memory from weak bit failure. In accordance with at least one embodiment, a method of using a dedicated row of bit cells in a memory array is provided wherein each bit in the row controls the low power state of a respective column in the array. A special control signal is used to access the word line, and the word line is outside of the regular word line address space. A mechanism is provided to designate the weak bit column and set the control bit corresponding to that particular column to disable the drowsy/low power state for that column.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: April 19, 2016
    Inventors: Ravindraraj Ramaraju, Jianan Yang, Mark W. Jetton, Thomas W. Liston, George P. Hoekstra, Andrew C. Russell
  • Publication number: 20160035433
    Abstract: A memory array with RAM and embedded ROM including multiple RAM cells, a ROM cell, and a ROM enable circuit. Each RAM cell has a RAM cell structure with a first and second power terminals and configured to operate as a RAM cell when the memory array is in a RAM mode. The ROM cell has the same RAM cell structure in which at least one transistor is modified to cause the ROM cell to have a predetermined logic state. The ROM enable circuit enables bit lines of the ROM cell to control supply voltages provided to the power terminals of the RAM cells so that they settle to predetermined logic states in a ROM mode. The modified transistor has a pseudo transistor structure having a modified substrate that operates as a resistance, such as a doping region in the substrate having the same polarity type as the substrate.
    Type: Application
    Filed: July 30, 2014
    Publication date: February 4, 2016
    Inventors: JIANAN YANG, SCOTT I. REMINGTON, SHAYAN ZHANG
  • Patent number: 9123545
    Abstract: A semiconductor device includes a parasitic silicon-controlled rectifier (SCR) and a first transistor. The parasitic SCR includes a parasitic pnp bipolar junction transistor (BJT) and a parasitic npn BJT. The first transistor is coupled between a first power supply node and an emitter of the parasitic pnp BJT. The first transistor includes a first terminal coupled to the first power supply node, a second terminal coupled to the emitter of the parasitic pnp BJT, and a control terminal. The first transistor is not positioned between a base of the pnp BJT and the first power supply node. The first transistor limits current conducted by the parasitic pnp BJT following a single-event latch-up (SEL) event.
    Type: Grant
    Filed: February 24, 2014
    Date of Patent: September 1, 2015
    Inventors: Jianan Yang, James D. Burnett, Brad J. Garni, Thomas W. Liston
  • Patent number: 9026808
    Abstract: In accordance with at least one embodiment, memory power gating at word level is provided. In accordance with at least one embodiment, a word level power-gating technique, which is enabled by adding an extra control bit to each subarray (e.g., each word, each row, each wordline, each bitline, each portion of an array, etc.) of a memory array, provides fine-grained power reduction for a memory array. In accordance with at least one embodiment, a gating transistor is provided for each subarray (e.g., each word, each row, each wordline, each bitline, each portion of an array, etc.).
    Type: Grant
    Filed: April 26, 2012
    Date of Patent: May 5, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jianan Yang, Mark W. Jetton, Thomas W. Liston
  • Patent number: 8995178
    Abstract: An integrated circuit includes first and second memory cells including a first pull-up transistor each having a body tie coupled to respective first and second well bias voltages. Drain electrodes of the first and second pull-up transistors are coupled to a first true bit line and a first complementary bit line, respectively. A second memory cell includes first and second pull-up transistors each having a body tie coupled to the second and first well bias voltages, respectively. Drain electrodes of the first and second pull-up transistors are coupled to a second true bit line and a second complementary bit line, respectively. The first well bias voltage is lower than the second well bias voltage during a Read-Only Memory (ROM) mode, and the first well bias voltage is the same as the second well bias voltage during a Static Random Access Memory (SRAM) mode.
    Type: Grant
    Filed: October 31, 2013
    Date of Patent: March 31, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jianan Yang, Brad J. Garni, Mark W. Jetton
  • Patent number: 8766703
    Abstract: A sensor circuit performs a method for sensing on-chip characteristics. The method includes generating a first voltage using a drive current through a first set of transistors that are operating in saturation mode and generating a second voltage using subthreshold leakage current from a second set of transistors that are in subthreshold mode. The method further includes comparing the second voltage to the first voltage to sense an on-chip characteristic. The sensed on-chip characteristic can be temperature and/or gate length variation.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: July 1, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jianan Yang, James D. Burnett, Mark W. Jetton, Thomas W. Liston
  • Publication number: 20140167102
    Abstract: A semiconductor device includes a parasitic silicon-controlled rectifier (SCR) and a first transistor. The parasitic SCR includes a parasitic pnp bipolar junction transistor (BJT) and a parasitic npn BJT. The first transistor is coupled between a first power supply node and an emitter of the parasitic pnp BJT. The first transistor includes a first terminal coupled to the first power supply node, a second terminal coupled to the emitter of the parasitic pnp BJT, and a control terminal. The first transistor is not positioned between a base of the pnp BJT and the first power supply node. The first transistor limits current conducted by the parasitic pnp BJT following a single-event latch-up (SEL) event.
    Type: Application
    Filed: February 24, 2014
    Publication date: June 19, 2014
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: JIANAN YANG, JAMES D. BURNETT, BRAD J. GARNI, THOMAS W. LISTON
  • Patent number: 8685800
    Abstract: A technique for addressing single-event latch-up (SEL) in a semiconductor device includes determining a location of a parasitic silicon-controlled rectifier (SCR) in an integrated circuit design of the semiconductor device. In this case, the parasitic SCR includes a parasitic pnp bipolar junction transistor (BJT) and a parasitic npn BJT. The technique also includes incorporating a first transistor between a first power supply node and an emitter of the parasitic pnp BJT in the integrated circuit design. The first transistor includes a first terminal coupled to the first power supply node, a second terminal coupled to the emitter of the parasitic pnp BJT, and a control terminal. The first transistor is not positioned between a base of the pnp BJT and the first power supply node. The first transistor limits current conducted by the parasitic pnp bipolar junction transistor following an SEL.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: April 1, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jianan Yang, James D. Burnett, Brad J. Garni, Thomas W. Liston, Huy Van Pham
  • Publication number: 20140027810
    Abstract: A technique for addressing single-event latch-up (SEL) in a semiconductor device includes determining a location of a parasitic silicon-controlled rectifier (SCR) in an integrated circuit design of the semiconductor device. In this case, the parasitic SCR includes a parasitic pnp bipolar junction transistor (BJT) and a parasitic npn BJT. The technique also includes incorporating a first transistor between a first power supply node and an emitter of the parasitic pnp BJT in the integrated circuit design. The first transistor includes a first terminal coupled to the first power supply node, a second terminal coupled to the emitter of the parasitic pnp BJT, and a control terminal. The first transistor is not positioned between a base of the pnp BJT and the first power supply node. The first transistor limits current conducted by the parasitic pnp bipolar junction transistor following an SEL.
    Type: Application
    Filed: July 27, 2012
    Publication date: January 30, 2014
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Jianan Yang, James D. Burnett, Brad J. Garni, Thomas W. Liston, Huy Van Pham
  • Patent number: 8631292
    Abstract: A flip-flop circuit includes a master latch, a master/slave gate, a slave latch, a slave gate, a feedback latch, and a master gate. The master latch has an input and an output. The master/slave gate has an input coupled to the output of the master latch and an output. The slave latch has input coupled to the output of the master/slave gate and an output. The slave gate has input coupled to the output of the slave latch and an output. The has an input coupled to the output of the slave gate and an output. The master gate has an input coupled to the output of the feedback latch and an output coupled to the input of the master latch.
    Type: Grant
    Filed: August 29, 2011
    Date of Patent: January 14, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jianan Yang, Gary R. Morrison
  • Patent number: 8575962
    Abstract: An integrated circuit comprises logic circuitry having a plurality of signal paths. A signal path of the plurality of signal paths has a propagation delay greater than a propagation delay of any other signal path of the plurality of signal paths. The signal path includes a plurality of components. The plurality of components is provided with a higher power supply voltage than any other signal path of the plurality of signal paths.
    Type: Grant
    Filed: August 29, 2011
    Date of Patent: November 5, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jianan Yang, Stephen G. Jamison, David L. Medlock, Gary Waugh
  • Publication number: 20130290753
    Abstract: In accordance with at least one embodiment, column level power control granularity is provided to control a low power state of a memory using a drowsy column control bit to control the low power state at an individual column level to protect the memory from weak bit failure. In accordance with at least one embodiment, a method of using a dedicated row of bit cells in a memory array is provided wherein each bit in the row controls the low power state of a respective column in the array. A special control signal is used to access the word line, and the word line is outside of the regular word line address space. A mechanism is provided to designate the weak bit column and set the control bit corresponding to that particular column to disable the drowsy/low power state for that column.
    Type: Application
    Filed: November 29, 2012
    Publication date: October 31, 2013
    Inventors: Ravindraraj Ramaraju, Jianan Yang, Mark W. Jetton, Thomas W. Liston, George P. Hoekstra, Andrew C. Russell
  • Publication number: 20130290750
    Abstract: In accordance with at least one embodiment, memory power gating at word level is provided. In accordance with at least one embodiment, a word level power-gating technique, which is enabled by adding an extra control bit to each subarray (e.g., each word, each row, each wordline, each bitline, each portion of an array, etc.) of a memory array, provides fine-grained power reduction for a memory array. In accordance with at least one embodiment, a gating transistor is provided for each subarray (e.g., each word, each row, each wordline, each bitline, each portion of an array, etc.).
    Type: Application
    Filed: April 26, 2012
    Publication date: October 31, 2013
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Jianan Yang, Mark W. Jetton, Thomas W. Liston
  • Patent number: 8446176
    Abstract: An integrated circuit ECO base cell module is formed with PMOS and NMOS gate electrode structures and power supply lines that are electrically separated from one another up to the second metal (M2) layer in a fixed circuit structure that may be reconfigured with one or more conductor elements formed above the M2 layer to form a predetermined circuit function.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: May 21, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jianan Yang, Darrin L. Hutchinson, Stephen G. Jamison
  • Publication number: 20130049807
    Abstract: An integrated circuit comprises logic circuitry having a plurality of signal paths. A signal path of the plurality of signal paths has a propagation delay greater than a propagation delay of any other signal path of the plurality of signal paths. The signal path includes a plurality of components. The plurality of components is provided with a higher power supply voltage than any other signal path of the plurality of signal paths.
    Type: Application
    Filed: August 29, 2011
    Publication date: February 28, 2013
    Inventors: JIANAN YANG, Stephen G. Jamison, David L. Medlock, Gary Waugh
  • Publication number: 20130049836
    Abstract: A flip-flop circuit includes a master latch, a master/slave gate, a slave latch, a slave gate, a feedback latch, and a master gate. The master latch has an input and an output. The master/slave gate has an input coupled to the output of the master latch and an output. The slave latch has input coupled to the output of the master/slave gate and an output. The slave gate has input coupled to the output of the slave latch and an output. The has an input coupled to the output of the slave gate and an output. The master gate has an input coupled to the output of the feedback latch and an output coupled to the input of the master latch.
    Type: Application
    Filed: August 29, 2011
    Publication date: February 28, 2013
    Inventors: Jianan Yang, Gary R. Morrison