Abstract: A package includes a housing assembly and a drawer assembly. The housing assembly is provided with an open cavity, and the housing assembly has an unlocking member and a blocking surface. The drawer assembly is configured to carry an article and is engaged with the open cavity to receive the article in the open cavity. The drawer assembly includes an elastic member. When the elastic member abuts against the blocking surface, the blocking surface prevents the drawer assembly from sliding out of the open cavity. When a force is applied to the unlocking member to deform the elastic member, the elastic member is misaligned with the blocking surface so that the drawer assembly can slide out of the open cavity.

Abstract: A package includes a housing assembly and a drawer assembly. The housing assembly is provided with an open cavity, and the housing assembly has an unlocking member and a blocking surface. The drawer assembly is configured to carry an article and is engaged with the open cavity to receive the article in the open cavity. The drawer assembly includes an elastic member. When the elastic member abuts against the blocking surface, the blocking surface prevents the drawer assembly from sliding out of the open cavity. When a force is applied to the unlocking member to deform the elastic member, the elastic member is misaligned with the blocking surface so that the drawer assembly can slide out of the open cavity.

Abstract: The present invention discloses an information management method and system for IC tests, and a storage medium. The method comprises steps of: providing test data generated by performing an IC test by an IC test platform, the IC test platform being an IC test platform having more than one stage, each stage of the IC test platform comprising a plurality of test devices: providing resource data related to the IC test, other than the test data; and analyzing the IC test according to the test data of the IC test and the resource data, to obtain result data related to the IC test. In this way, the present invention can provide technical support for utilizing the value of test data generated in IC tests.

Abstract: The present invention relates to an optimization method for an integrated circuit wafer test, which is applied in an integrated circuit wafer test process. By means of pre-specifying and storing coordinates of a die to be tested on a wafer in a test system, then testing the pre-specified die according to a design map by means of a test process, and adjusting in real time a range of pre-specified coordinates according to a test result of a current die, a desired test coordinate map is finally obtained so as to cover the maximum number of fail dies in an optimized solution, thereby reducing test time, improving testing efficiency, reducing the frequency of testing hardware usage and increasing service life. By means of calculating a suitable coverage number in the present invention, a smaller number of fail chips that reach a package will also be obtained without increasing the cost of the package. At the same time, the number of probe card tests is reduced, and the hardware service life is increased.

Abstract: A configuration and testing method and system for an FPGA chip using a bumping process are disclosed, the method includes creating configuration files for an FPGA chip under test and storing them in a memory; reading, by a master FPGA, a configuration code stream of corresponding configuration codes from the mass memory, configuring the FPGA chip under test via an external test interface, and determining whether the configuration is successful; if the configuration is successful, converting the configuration code stream into a test signal source file that is recognizable, executable and reusable by multiple pieces of test equipment by a developed algorithm and a conversion tool; and automatically loading the test signal source file onto the FPGA chip under test in real time by advanced test equipment.

Abstract: The present invention discloses an information management method and system for IC tests, and a storage medium. The method comprises steps of: providing test data generated by performing an IC test by an IC test platform, the IC test platform being an IC test platform having more than one stage, each stage of the IC test platform comprising a plurality of test devices: providing resource data related to the IC test, other than the test data; and analyzing the IC test according to the test data of the IC test and the resource data, to obtain result data related to the IC test. In this way, the present invention can provide technical support for utilizing the value of test data generated in IC tests.

Abstract: A configuration and testing method and system for an FPGA chip using a bumping process are disclosed, the method includes creating configuration files for an FPGA chip under test and storing them in a memory; reading, by a master FPGA, a configuration code stream of corresponding configuration codes from the mass memory, configuring the FPGA chip under test via an external test interface, and determining whether the configuration is successful; if the configuration is successful, converting the configuration code stream into a test signal source file that is recognizable, executable and reusable by multiple pieces of test equipment by a developed algorithm and a conversion tool; and automatically loading the test signal source file onto the FPGA chip under test in real time by advanced test equipment.

Abstract: An IEEE 1149.1 standard based testing method used in packaging is disclosed. The method includes adding a TRD pin to each of n devices up to the IEEE 1149.1 standard. The TRD pins of the n devices are connected together to a common output terminal which is connected to a testing system. The first to m-th ones of the devices are tested by connecting the TDO and TRD pins of the m-th device and disconnecting the TDO and TRD pins of any one of the n devices other than the m-th, wherein m is a natural number that is smaller than or equal to n.