Patents by Inventor Jianfeng Gao
Jianfeng Gao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250120108Abstract: A method for fabricating a GAA nanosheet structure, comprising: forming at least two channel layers and at least one sacrificial layer alternately stacked on a substrate to form a channel stack; forming, on the substrate, a dummy gate astride the channel stack; forming a first sidewall on a surface of the dummy gate; etching the sacrificial layer to form a recess at a side surface of the channel stack; forming a second sidewall within the recess; forming a source and a drain at two sides of the channel stack; in response to a channel layer being in contact with the dummy gate, etching the dummy gate and the channel layer to expose the at least one sacrificial layer, and then etching the at least one sacrificial layer to form a space for manufacturing a surrounding gate; and forming a metallic surrounding gate in the space.Type: ApplicationFiled: November 27, 2023Publication date: April 10, 2025Inventors: Na ZHOU, Junjie LI, Jianfeng GAO, Tao YANG, Junfeng LI, Jun LUO
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Publication number: 20250081530Abstract: A semiconductor device and a method for manufacturing the same. The method comprises: providing a substrate; forming a fin, a dummy gate, a first spacer, and a hard mask on a surface of the substrate; etching the substrate to form a groove located directly beneath the fin and running through a second spacer; forming, in the groove, a filling layer made of an insulating dielectric material, and thermal conductivity of the insulating dielectric material is higher than that of the substrate; removing the second spacer through etching; removing two opposite ends of each sacrificial layer to form cavities; filling the cavities to form inner spacers; forming a source and a drain on the substrate; forming a first dielectric layer; planarizing the first dielectric layer to expose the dummy gate; removing the dummy gate to release a channel comprising conductive nanosheets; forming a surrounding gate surrounding the conductive nanosheets.Type: ApplicationFiled: November 27, 2023Publication date: March 6, 2025Inventors: Junjie LI, Enxu LIU, Na ZHOU, Jianfeng GAO, Junfeng LI, Yongliang LI, Jun LUO, Wenwu WANG
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Patent number: 12242971Abstract: This document relates to training of machine learning models such as neural networks. One example method involves providing a machine learning model having one or more layers and associated parameters and performing a pretraining stage on the parameters of the machine learning model to obtain pretrained parameters. The example method also involves performing a tuning stage on the machine learning model by using labeled training samples to tune the pretrained parameters. The tuning stage can include performing noise adjustment of the labeled training examples to obtain noise-adjusted training samples. The tuning stage can also include adjusting the pretrained parameters based at least on the labeled training examples and the noise-adjusted training examples to obtain adapted parameters. The example method can also include outputting a tuned machine learning model having the adapted parameters.Type: GrantFiled: January 29, 2020Date of Patent: March 4, 2025Assignee: Microsoft Technology Licensing, LLCInventors: Xiaodong Liu, Jianfeng Gao, Pengcheng He, Weizhu Chen
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Publication number: 20250063713Abstract: The present disclosure provides a memory with a three-dimensional vertical structure and a manufacturing method. The memory includes: a semiconductor substrate, a first isolation layer, a first transistor and a second transistor. The first transistor includes a first source layer, a second isolation layer, a first drain layer, a third isolation layer, and a first through hole penetrating to the first source layer. A first active layer, a first gate dielectric layer and a first gate layer are on an inner sidewall of the first through hole. The second transistor includes a fourth isolation layer, a second source layer, a fifth isolation layer, and a second through hole penetrating to the first gate layer. A second active layer, a second gate dielectric layer and a second gate layer are on an inner sidewall of the second through hole. The second through hole is surrounded by the first through hole.Type: ApplicationFiled: August 9, 2024Publication date: February 20, 2025Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCESInventors: Jianfeng GAO, Weibing LIU, Junjie LI, Na ZHOU, Tao Yang, Junfeng LI, Jun LUO
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Patent number: 12223269Abstract: A method for training a language model comprises (a) receiving vectorized training data as input to a multitask pretraining problem; (b) generating modified vectorized training data based on the vectorized training data, according to an upstream data embedding; (c) emitting pretraining output based on the modified vectorized training data, according to a downstream data embedding equivalent to the upstream data embedding; and (d) adjusting the upstream data embedding and the downstream data embedding by computing, based on the pretraining output, a gradient of the upstream data embedding disentangled from a gradient of the downstream data embedding, thereby advancing the multitask pretraining problem toward a pretrained state.Type: GrantFiled: May 18, 2022Date of Patent: February 11, 2025Assignee: Microsoft Technology Licensing, LLCInventors: Pengcheng He, Jianfeng Gao, Weizhu Chen
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Publication number: 20250048324Abstract: An example positioning method includes sending, by a first device, sidelink control information (SCI) to a second device, where the SCI comprises time-frequency resource information of a reference signal, and the reference signal is used for positioning The first device sends the reference signal to the second device and receives a response message sent by the second device, where the response message comprises location information determined by the second device based on the reference signal.Type: ApplicationFiled: October 23, 2024Publication date: February 6, 2025Inventors: Xin GAO, Shunshun SHANG, Mengting LIU, Jianfeng LI, Cheng LI
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Publication number: 20250040226Abstract: The present disclosure provides a semiconductor device and a method of manufacturing a semiconductor device. The semiconductor device includes: a substrate; an insulating layer provided with a plurality of trenches extending in a first direction; a first electrode layer and a second electrode layer, where a spacing region is provided between the first electrode layer and the second electrode layer; a semiconductor layer covering bottom portions and sidewalls of all channel trenches, where the channel trenches are at least a part of trench bodies of the trenches located in the spacing region; a gate dielectric layer covering a surface of the semiconductor layer in the channel trenches on a side away from the bottom portions and the sidewalls of the channel trenches; a gate layer, where at least a part of the channel trenches are fully filled with the gate layer.Type: ApplicationFiled: July 26, 2024Publication date: January 30, 2025Inventors: Junjie LI, Gaobo Xu, Na Zhou, Chenchen Zhang, Jianfeng Gao, Yihong Lu, Tao Yang, Junfeng Li, Jun Luo, Rui Chen
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Patent number: 12205341Abstract: The present invention relates to a neural network-based high-resolution image restoration method and system, including: performing feature extraction on a target frame in a network input to obtain a first feature, performing feature extraction on a first frame and an adjacent frame and an optical flow between the first frame and the adjacent frame to obtain a second feature, and concatenating the first feature and the second feature to obtain a shallow layer feature; performing feature extraction and refinement on the shallow layer feature to obtain a plurality of output first features and a plurality of output second features; performing feature decoding on the plurality of output second features, and concatenating decoded features along channel dimensionality to obtain features; and performing weight distribution on the features to obtain final features, and restoring an image. The present invention can effectively help to improve image quality.Type: GrantFiled: January 7, 2021Date of Patent: January 21, 2025Assignee: SOOCHOW UNIVERSITYInventors: Jianling Hu, Lihang Gao, Dong Liao, Jianfeng Yang, Honglong Cao
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Publication number: 20250006822Abstract: A method for manufacturing a gate-all-around TFET device. The method comprises: forming, on a substrate, a channel stack comprising channel layer(s) and sacrificial layer(s) that alternate with each other; forming, on the substrate, a dummy gate astride the channel stack; forming a first spacer at a surface of the dummy gate; etching the sacrificial layer(s) to form recesses on side surfaces of the channel stack; forming second spacers in the recesses, respectively; fabricating a source and a drain separately, where a region for fabricating the source is shielded by a dielectric material when fabricating the drain, and a region for fabricating the drain is shielded by another dielectric material when fabricating the source; etching the dummy gate and the sacrificial layer(s) to form a space for a surrounding gate; and fabricating a surrounding dielectric-metal gate in the space.Type: ApplicationFiled: November 27, 2023Publication date: January 2, 2025Inventors: Na Zhou, Junjie Li, Jianfeng Gao, Tao Yang, Junfeng Li, Jun Luo
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Publication number: 20240419960Abstract: Generally discussed herein are devices, systems, and methods for backpropagation of a discrete latent variable.Type: ApplicationFiled: June 19, 2023Publication date: December 19, 2024Inventors: Liyuan LIU, Chengyu DONG, Xiaodong LIU, Bin YU, Jianfeng GAO
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Publication number: 20240362418Abstract: A technique supplements a language model with knowledge information retrieved from external sources. The technique operates by: receiving a query; receiving knowledge information based on the query; generating original model-input information that includes the query and the knowledge information; and presenting the original model-input information to the language model. The technique further includes: receiving an original response from the language model; generating a usefulness measure that identifies usefulness of the original response; and determining whether the usefulness measure satisfies a prescribed test. Upon determining that the usefulness measure does not satisfy the test, the technique includes: generating revised model-input information that includes feedback information; presenting the revised model-input information to the language model; and receiving a revised response from the language model.Type: ApplicationFiled: April 28, 2023Publication date: October 31, 2024Applicant: Microsoft Technology Licensing, LLCInventors: Baolin PENG, Michel GALLEY, Hao CHENG, Pengcheng HE, Nguyen Hung BACH, Weizhu CHEN, Jianfeng GAO
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Publication number: 20240346295Abstract: This document relates to architectures and training procedures for multi-task machine learning models, such as neural networks. One example method involves providing a multi-task machine learning model having one or more shared layers and two or more task-specific layers. The method can also involve performing a pretraining stage on the one or more shared layers using one or more unsupervised prediction tasks.Type: ApplicationFiled: May 3, 2024Publication date: October 17, 2024Applicant: Microsoft Technology Licensing, LLCInventors: Weizhu CHEN, Pengcheng HE, Xiaodong LIU, Jianfeng GAO
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Publication number: 20240311656Abstract: A technique performs the task of knowledge-graph completion in a manner that is both scalable and resource efficient. In some implementations, the technique identifies a source entity having a source-target relation that connects the source entity to a yet-to-be-determined target entity. The technique also identifies a source-entity data item that provides a passage of source-entity text pertaining to the source entity. The technique uses a machine-trained encoder model to map the source-entity data item to source-entity encoded information. The technique then predicts an identity of the target entity based on the source-entity encoded information, and based on predicate encoded information that encodes the source-target relation. In some implementations, the technique also predicts the target entity based on a consideration of one or more neighboring entities that are connected to the source entity and their respective source-to-neighbor relations.Type: ApplicationFiled: March 16, 2023Publication date: September 19, 2024Applicant: Microsoft Technology Licensing, LLCInventors: Xiaodong LIU, Jian JIAO, Hao CHENG, Sanxing CHEN, Jianfeng GAO
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Publication number: 20240281705Abstract: The disclosed concepts relate to pretraining of machine learning models. One example method involves performing separate optimization of a first machine learning model and a second machine learning model. The first machine learning model can be optimized based at least on first predictions and the second machine learning model can be optimized based at least on second predictions. The first predictions can represent predictions of masked values in first sequences of values values, and the second predictions can represent whether or not the first values were replaced with different values predicted by the first machine learning model.Type: ApplicationFiled: June 21, 2023Publication date: August 22, 2024Applicant: Microsoft Technology Licensing, LLCInventors: Xiaodong LIU, Chengyu DONG, Lucas LIU, Hao CHENG, Jianfeng GAO
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Patent number: 12061876Abstract: Systems and methods are provided for facilitating the building and use of natural language understanding models. The systems and methods identify a plurality of tokens and use them to generate one or more pre-trained natural language models using a transformer. The transformer disentangles the content embedding and positional embedding in the computation of its attention matrix. Systems and methods are also provided to facilitate self-training of the pre-trained natural language model by utilizing multi-step decoding to better reconstruct masked tokens and improve pre-training convergence.Type: GrantFiled: December 9, 2022Date of Patent: August 13, 2024Assignee: Microsoft Technology Licensing, LLCInventors: Pengcheng He, Xiaodong Liu, Jianfeng Gao, Weizhu Chen
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Patent number: 12032627Abstract: Systems and methods are provided for determining a response to a query in a dialog. An entity extractor extracts rules and conditions associated with the query and determines a particular task. The disclosed technology generates a transformer-based dialog embedding by pre-training a transformer using dialog corpora including a plurality of tasks. A task-specific classifier generates a first set of candidate responses based on rules and conditions associated with the task. The transformer-based dialog embedding generates a second set of candidate responses to the query. The classifier accommodates changes made to a task by an interactive dialog editor as machine teaching. A response generator generates a response based on the first and second sets of candidate responses using an optimization function.Type: GrantFiled: November 15, 2021Date of Patent: July 9, 2024Assignee: Microsoft Technology Licensing, LLCInventors: Jinchao Li, Lars H. Liden, Baolin Peng, Thomas Park, Swadheen Kumar Shukla, Jianfeng Gao
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Publication number: 20240202583Abstract: A computing device is provided including a processor configured to execute a transformer including an encoder having a global layer configured to receive tokenized embeddings for each of a plurality of tokens in a local input sequence and compute a global self-attention vector for each of the tokenized embeddings. The encoder further includes a local layer configured to receive each global self-attention vector from the global layer and compute local self-attention for each local input sequence, and add and normalize the global self-attention vector with the local self-attention vector to thereby produce an encoder representation including a self-attention vector for each local input sequence that includes both global self-attention values and local self-attention values. The transformer is configured to output a prediction for the global input sequence based on the encoder representation of each of the local input sequences of the global input sequence.Type: ApplicationFiled: March 21, 2023Publication date: June 20, 2024Applicant: Microsoft Technology Licensing, LLCInventors: Xiaodong LIU, Jian JIAO, Simiao ZUO, Jianfeng GAO
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Publication number: 20240194737Abstract: A method for manufacturing a semiconductor and a semiconductor. The method includes: providing a substrate, wherein an active region trench is on the substrate, and a channel stack of a gate-all-around transistor is formed in the active region trench, the active region trench is divided into a source trench and a drain trench by the channel stack; epitaxially growing a source crystal structure in the source trench and a drain crystal structure in the drain trench, and stopping epitaxial growth before crystal planes with different orientations of the source crystal structure intersect and crystal planes with different orientations of the drain crystal structure intersect; and filling gaps between the crystal planes with different orientations of the source crystal structure and the drain crystal structure by using an isotropic metal material, and forming a source and a drain of the gate-all-around transistor in the source trench and the drain trench, respectively.Type: ApplicationFiled: December 5, 2023Publication date: June 13, 2024Inventors: Junjie LI, Enxu LIU, Na ZHOU, Jianfeng GAO, Junfeng LI, Jun LUO, Wenwu WANG
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Patent number: D1060017Type: GrantFiled: September 19, 2024Date of Patent: February 4, 2025Inventor: Jianfeng Gao
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Patent number: D1068039Type: GrantFiled: October 23, 2024Date of Patent: March 25, 2025Inventor: Jianfeng Gao