Abstract: The present disclosure provides a memory with a three-dimensional vertical structure and a manufacturing method. The memory includes: a semiconductor substrate, a first isolation layer, a first transistor and a second transistor. The first transistor includes a first source layer, a second isolation layer, a first drain layer, a third isolation layer, and a first through hole penetrating to the first source layer. A first active layer, a first gate dielectric layer and a first gate layer are on an inner sidewall of the first through hole. The second transistor includes a fourth isolation layer, a second source layer, a fifth isolation layer, and a second through hole penetrating to the first gate layer. A second active layer, a second gate dielectric layer and a second gate layer are on an inner sidewall of the second through hole. The second through hole is surrounded by the first through hole.

Abstract: The present disclosure provides a semiconductor device and a method of manufacturing a semiconductor device. The semiconductor device includes: a substrate; an insulating layer provided with a plurality of trenches extending in a first direction; a first electrode layer and a second electrode layer, where a spacing region is provided between the first electrode layer and the second electrode layer; a semiconductor layer covering bottom portions and sidewalls of all channel trenches, where the channel trenches are at least a part of trench bodies of the trenches located in the spacing region; a gate dielectric layer covering a surface of the semiconductor layer in the channel trenches on a side away from the bottom portions and the sidewalls of the channel trenches; a gate layer, where at least a part of the channel trenches are fully filled with the gate layer.

Abstract: An optical fiber adapter (10) comprises: a housing (1), a front portion of the housing (1) is provided with at least two accommodating cavities (19) which penetrate in a front-rear direction, are arranged sided by side, and are closed circumferentially, and a rear portion of the housing (1) is provided with a mounting base (14); at least two optical fiber plugs (2) provided on the mounting base (14), each optical fiber plug (2) comprises a positioning member (21), a ferrule (22) fixed to the positioning member (21) and extending forwardly, an optical fiber (23) exposed to a front end of the ferrule (22), a sleeve (24) fitted on an outer periphery of the ferrule (22) and a positioning cylinder (25) further sheathed on an outer periphery of the sleeve (24), a front end of the positioning cylinder (25) extends forwardly into the accommodating cavity (19), a rear end of the positioning cylinder (25) is fixed to the positioning member (21), an outer periphery of the positioning member (21) is provided with a first

Abstract: An optical fiber adapter (10) comprises: a housing (1), a front portion of the housing (1) is provided with at least two accommodating cavities (19) which penetrate in a front-rear direction, are arranged sided by side, and are closed circumferentially, and a rear portion of the housing (1) is provided with a mounting base (14); at least two optical fiber plugs (2) provided on the mounting base (14), each optical fiber plug (2) comprises a positioning member (21), a ferrule (22) fixed to the positioning member (21) and extending forwardly, an optical fiber (23) exposed to a front end of the ferrule (22), a sleeve (24) fitted on an outer periphery of the ferrule (22) and a positioning cylinder (25) further sheathed on an outer periphery of the sleeve (24), a front end of the positioning cylinder (25) extends forwardly into the accommodating cavity (19), a rear end of the positioning cylinder (25) is fixed to the positioning member (21), an outer periphery of the positioning member (21) is provided with a first

Abstract: A method of improving a design rule fixing process comprises receiving an integrated circuit design, including layout elements, and identifying a plurality of design rule violations in the integrated circuit design. The process then identifies a plurality of possible actions, each action comprising fixing a design rule. The process then uses a deep learning algorithm to select an action, the action representing fixing of a particular design rule violation. The process then comprises applying a first patch, based on the order returning to step (b) to select a next patch to apply.

Abstract: An organic light-emitting diode display panel for fingerprint recognition includes a glass substrate, a pixel layer, and a transparent substrate, which are laminated; the pixel layer includes a plurality of pixel units arranged on the glass substrate in arrays, wherein the plurality of pixel units are configured to emit light of multiple colors which are combined to form a colorful image; the transparent substrate includes a first side and a second side, which are disposed opposite to each other, the first side is fitted on the pixel layer, a plurality of light receiving units are arranged on a surface of the second side, and an orthographic projection of each light receiving unit on the transparent substrate is located in a gap between the adjacent pixel units. An electronic device is also provided.

Abstract: An organic light-emitting diode display panel for fingerprint recognition includes a plurality of pixel areas arranged in arrays, the pixel area includes a pixel unit and a fingerprint recognition unit, which are adjacent to each other, the pixel unit is configured to emit colorful image light, the fingerprint recognition unit comprises a sensing light emitting module and a sensing light receiving module, the sensing light emitting module is configured to emit sensing light to a finger, and the sensing light receiving module is configured to receive the sensing light reflected by the finger and convert a light signal of the sensing light into an electric signal. An electronic device is also provided.

Abstract: An organic light-emitting diode display panel for fingerprint recognition includes a glass substrate, a pixel layer, and a transparent substrate, which are laminated; the pixel layer includes a plurality of pixel units arranged on the glass substrate in arrays, wherein the plurality of pixel units are configured to emit light of multiple colors which are combined to form a colorful image; the transparent substrate includes a first side and a second side, which are disposed opposite to each other, the first side is fitted on the pixel layer, a plurality of light receiving units are arranged on a surface of the second side, and an orthographic projection of each light receiving unit on the transparent substrate is located in a gap between the adjacent pixel units. An electronic device is also provided.

Abstract: An OLED display panel for fingerprint recognition includes a plurality of pixel areas arranged in arrays, the pixel area includes a pixel unit and a fingerprint recognition unit, which are adjacent to each other, the pixel unit is configured to emit light of different colors, the fingerprint recognition unit comprises a sensing light emitting module and a sensing light receiving module, the sensing light emitting module is configured to emit sensing light to a finger, and the sensing light receiving module is configured to receive the sensing light reflected by the finger and convert a light signal of the sensing light into an electric signal. An electronic device having the OLED display panel is also provided.

Abstract: An organic light-emitting diode display panel for fingerprint recognition includes a plurality of pixel areas arranged in arrays, the pixel area includes a pixel unit and a fingerprint recognition unit, which are adjacent to each other, the pixel unit is configured to emit colorful image light, the fingerprint recognition unit comprises a sensing light emitting module and a sensing light receiving module, the sensing light emitting module is configured to emit sensing light to a finger, and the sensing light receiving module is configured to receive the sensing light reflected by the finger and convert a light signal of the sensing light into an electric signal. An electronic device is also provided.

Abstract: A method, system or computer usable program product for preventing odd cycles caused by design modifications to a double patterning layout including utilizing a processor to identify a set of double patterning cycles in the layout for storage in a memory; receiving a set of design modifications to the layout; utilizing the processor to identify from the set of double patterning cycles a subset of double patterning cycles affected by the set of design modifications; utilizing the processor to identify from the set of design modifications a subset of design modifications which may cause odd cycles in the subset of double patterning cycles; and providing a notification of the subset of design modifications.

Abstract: Graph analysis for double pattern lithography is described. Layout shapes are decomposed into rectangles and a vertex is provided for each rectangle. Double pattern spacing conflicts are determined and shown as edges for the graph analysis. Odd cycles are used to identify double pattern lithography violations. Cycles can be completed with the addition of edges between vertices where stitches have been included in the layout. Edges between touching shapes do not count toward the odd count in the cycles. Fixes are included by increasing space or by rerouting. A portion of the layout can be incrementally changed and a local update of the graph analysis performed. Correct by construction layout is implemented by avoiding certain odd cycle prone layout routings.

Abstract: Graph analysis for double pattern lithography is described. Layout shapes are decomposed into rectangles and a vertex is provided for each rectangle. Double pattern spacing conflicts are determined and shown as edges for the graph analysis. Odd cycles are used to identify double pattern lithography violations. Cycles can be completed with the addition of edges between vertices where stitches have been included in the layout. Edges between touching shapes do not count toward the odd count in the cycles. Fixes are included by increasing space or by rerouting. A portion of the layout can be incrementally changed and a local update of the graph analysis performed. Correct by construction layout is implemented by avoiding certain odd cycle prone layout routings.

Abstract: One embodiment of the present invention provides a system that predicts manufacturing yield for a die within a semiconductor wafer. During operation, the system first receives a physical layout of the die. Next, the system partitions the die into an array of tiles. The system then computes systematic variations for a quality indicative value to describe a process parameter across the array of tiles based on the physical layout of the die. Next, the system applies a random variation for the quality indicative parameter to each tile in the array of tiles. Finally, the system obtains the manufacturing yield for the die based on both the systematic variations and the random variations.

Abstract: A bail type-unlocking device for an opto-electronic module, which pertains to an unlocking device for a hot pluggable type opto-electronic module in the optical communication field.

Abstract: An unlocking and resetting device for an opto-electronic module comprises a casing having a blind hole and a horizontal slide slot, and first and second mounting parts; an elastic piece; a shell; first springs; an insert block adapted to be inserted into the blind hole; a brake member adapted to be inserted and disposed in the horizontal slide slot; second springs; first and second pressing blocks adapted to be mounted onto first and second mounting parts; and a bail having a cam portion. The single-arm bail of the unlocking and resetting device can return the start position automatically without manual repositions.

Abstract: An unlocking and resetting device for an opto-electronic module comprises a casing having a blind hole and a horizontal slide slot, and first and second mounting parts; an elastic piece; a shell; first springs; an insert block adapted to be inserted into the blind hole; a brake member adapted to be inserted and disposed in the horizontal slide slot; second springs; first and second pressing blocks adapted to be mounted onto first and second mounting parts; and a bail having a cam portion. The single-arm bail of the unlocking and resetting device can return the start position automatically without manual repositions.

Abstract: A bail type-unlocking device for an opto-electronic module, which pertains to an unlocking device for a hot pluggable type opto-electronic module in the optical communication field.

Abstract: The use of smooth post-ECP topography (instead of final chip topography) as an objective during dummy filling enables a computationally efficient model-based dummy filling solution for copper while maintaining solution quality. A layout can be divided into tiles and the “case” of each tile identified. Exemplary cases can include conformal fill, over fill, super fill, or super/over fill (if the ECP model cannot distinguish between super and over fill cases). One or more undesired tile cases can be converted to a desired tile case. Then, a height difference between tiles can be minimized. Dummy features can be inserted in the layout to perform the conversion and to minimize the height difference between tiles. Minimizing the CMP-effective density difference between tiles with ECP considerations can be performed to further improve planarization.

Abstract: A dimension of a conductive material in a semiconductor wafer is determined by a computer that treats as identical (a) volume of the conductive material which is proportional to an effective surface area of sidewalls of an insulative trench and (b) volume of the conductive material derived from geometry based on a predetermined amount by which width of a conductive trench (if present) in the conductive material differs from width of the insulative trench. In some embodiments, the computer computes the effective surface area as the product of trench depth and a layout parameter, either or both of which may be partially or wholly empirically determined from a test wafer containing several topographies. The computer computes the dimension assuming one topography and validates the assumption if a predetermined condition is met. If the condition is not met, the computer re-computes the dimension, assuming another topography.