Patents by Inventor Jianfeng Yang

Jianfeng Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250120108
    Abstract: A method for fabricating a GAA nanosheet structure, comprising: forming at least two channel layers and at least one sacrificial layer alternately stacked on a substrate to form a channel stack; forming, on the substrate, a dummy gate astride the channel stack; forming a first sidewall on a surface of the dummy gate; etching the sacrificial layer to form a recess at a side surface of the channel stack; forming a second sidewall within the recess; forming a source and a drain at two sides of the channel stack; in response to a channel layer being in contact with the dummy gate, etching the dummy gate and the channel layer to expose the at least one sacrificial layer, and then etching the at least one sacrificial layer to form a space for manufacturing a surrounding gate; and forming a metallic surrounding gate in the space.
    Type: Application
    Filed: November 27, 2023
    Publication date: April 10, 2025
    Inventors: Na ZHOU, Junjie LI, Jianfeng GAO, Tao YANG, Junfeng LI, Jun LUO
  • Publication number: 20250082666
    Abstract: A drug for the prevention or treatment of sepsis is provided. The drug comprises an exosome containing a circRNA MOTOR, and a nucleotide sequence corresponding to the circRNA MOTOR is shown in SEQ ID NO: 1.
    Type: Application
    Filed: November 21, 2024
    Publication date: March 13, 2025
    Applicant: SOUTHEAST UNIVERSITY
    Inventors: Wei HUANG, Haibo QIU, Ke FANG, Jianfeng XIE, Ling LIU, Yi YANG, Ran YANG
  • Patent number: 12245073
    Abstract: A congestion control method, apparatus and system, and a non-transitory computer-readable storage medium are disclosed. The congestion control method, which is applied to a first gateway, may include: monitoring node state information of a second gateway, where the second gateway is a collaboration gateway of the first gateway; and performing at least one of: in response to the node state information indicating a traffic overload of the second gateway, notifying a central gateway of the traffic overload of the second gateway, and sending a traffic collaboration request of the second gateway to an application server; or in response to the node state information indicating a service recovery of the second gateway, notifying the central gateway of the service recovery of the second gateway, and sending a service collaboration revocation request of the second gateway to the application server.
    Type: Grant
    Filed: January 13, 2021
    Date of Patent: March 4, 2025
    Assignee: ZTE Corporation
    Inventors: Kun Yang, Xiaoquan Hua, Jianfeng Ding
  • Patent number: 12234522
    Abstract: A method for controlling carbide network in a bearing steel wire rod by controlling cooling and rolling, comprises the following steps: rapidly rolling a bar to a wire rod and spinning it into a loose coil, controlling the rolling temperature at 780° C.-880° C.; and the spinning temperature at 750° C.-850° C.; carrying out on-line controlling cooling of continuous loose coils using EDC water bath austempering cooling process, controlling the cooling rate at 2.0° C./s-10° C./s, and controlling the final cooling temperature within 620-630° C.; after EDC water bath austempering cooling, using slow cooling under a cover, and the temperature is controlled to be 400° C.-500° C. when being removed out of the cover; after slow cooling, collecting coils, and cooling in air to the room temperature.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: February 25, 2025
    Assignees: JIANGYIN XINGCHENG GOLD MATERIALS CO., LTD, JIANGYIN XINGCHENG SPECIAL STEEL WORKS CO., LTD
    Inventors: Lin Zhang, Jianfeng Zhang, Changhe Lu, Yuehui Guan, Guozhong Li, Xiaohong Xu, Yun Bai, Hao Zong, Jiafeng He, De Chen, Zhen Huang, Jia Yang
  • Publication number: 20250063713
    Abstract: The present disclosure provides a memory with a three-dimensional vertical structure and a manufacturing method. The memory includes: a semiconductor substrate, a first isolation layer, a first transistor and a second transistor. The first transistor includes a first source layer, a second isolation layer, a first drain layer, a third isolation layer, and a first through hole penetrating to the first source layer. A first active layer, a first gate dielectric layer and a first gate layer are on an inner sidewall of the first through hole. The second transistor includes a fourth isolation layer, a second source layer, a fifth isolation layer, and a second through hole penetrating to the first gate layer. A second active layer, a second gate dielectric layer and a second gate layer are on an inner sidewall of the second through hole. The second through hole is surrounded by the first through hole.
    Type: Application
    Filed: August 9, 2024
    Publication date: February 20, 2025
    Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Jianfeng GAO, Weibing LIU, Junjie LI, Na ZHOU, Tao Yang, Junfeng LI, Jun LUO
  • Publication number: 20250052135
    Abstract: A wellhead automatic positioning method and a system of a plugging and perforating operation machine are provided. The method includes: determining a wellhead position, and acquiring standard positioning parameters of a boom according to the wellhead position and a tool string length, where the positioning parameters include a standard extension length L of the boom, a standard lifting length J, and an included angle ? between a projection of the boom and a wellhead; acquiring actual positioning parameters of the boom, where the actual positioning parameters include an actual length L? of the boom, an actual lifting length J?, and an initial angle ?? between the projection of the boom and the wellhead; and according to the standard positioning parameters and the actual positioning parameters of the boom, making the boom to extend and retract, lift and lower, and rotate to complete automatic positioning of the wellhead.
    Type: Application
    Filed: April 19, 2024
    Publication date: February 13, 2025
    Inventors: Jianbo LI, Liang BAI, Dawei ZHANG, Jianfeng YAO, Ziqiang KANG, Xijun JIANG, Enfeng YANG, Rui MAO, Bingwen WEI
  • Publication number: 20250052126
    Abstract: An integrated plugging and perforating operation system is provided, including an operation truck, a wellhead equipment pry, and a centralized control room. A mechanical mechanism and a power mechanism are arranged on a chassis of the operation truck. The mechanical mechanism includes a turntable assembly, where a telescopic arm assembly is installed on the turntable assembly, a mechanical arm assembly for logging operation is installed at an operating end of the telescopic arm assembly, and a logging winch assembly and a follow-up winch assembly are arranged at a counterweight end of the telescopic arm assembly to form a counter weight of the telescopic arm assembly. The power mechanism is configured for providing power output to the mechanical mechanism.
    Type: Application
    Filed: April 19, 2024
    Publication date: February 13, 2025
    Inventors: Jianbo LI, Ziqiang KANG, Jianfeng YAO, Xijun JIANG, Dawei ZHANG, Liang BAI, Teng LI, Haiquan LI, Enfeng YANG, Yaliang HU, Lin QI, Yonggang LV, Zhen YUAN, Qiujuan ZHANG, Rui MAO, Bingwen WEI
  • Patent number: 12218882
    Abstract: The present disclosure selects a node generating a periodic time slot request in a network to construct a set of periodic time slot request generation nodes, and constructs a time slot request cycle set; selects a node generating an aperiodic time slot request in the network to construct a set of aperiodic time slot request generation nodes, and constructs a time set of the aperiodic time slot request generation nodes; calculates a time slot contention scheduling parameter of each node in the set of the periodic time slot request generation nodes; and if no aperiodic time slot request arrives, allocates a time slot to each time slot requesting node during periodic time slot scheduling; or if an aperiodic time slot request, namely, a sporadic time slot request, arrives, performs rescheduling through hybrid time slot scheduling based on arrival time of the aperiodic time slot request.
    Type: Grant
    Filed: July 6, 2022
    Date of Patent: February 4, 2025
    Assignee: WUHAN UNIVERSITY
    Inventors: Jianfeng Yang, Chengcheng Guo
  • Publication number: 20250040226
    Abstract: The present disclosure provides a semiconductor device and a method of manufacturing a semiconductor device. The semiconductor device includes: a substrate; an insulating layer provided with a plurality of trenches extending in a first direction; a first electrode layer and a second electrode layer, where a spacing region is provided between the first electrode layer and the second electrode layer; a semiconductor layer covering bottom portions and sidewalls of all channel trenches, where the channel trenches are at least a part of trench bodies of the trenches located in the spacing region; a gate dielectric layer covering a surface of the semiconductor layer in the channel trenches on a side away from the bottom portions and the sidewalls of the channel trenches; a gate layer, where at least a part of the channel trenches are fully filled with the gate layer.
    Type: Application
    Filed: July 26, 2024
    Publication date: January 30, 2025
    Inventors: Junjie LI, Gaobo Xu, Na Zhou, Chenchen Zhang, Jianfeng Gao, Yihong Lu, Tao Yang, Junfeng Li, Jun Luo, Rui Chen
  • Patent number: 12205341
    Abstract: The present invention relates to a neural network-based high-resolution image restoration method and system, including: performing feature extraction on a target frame in a network input to obtain a first feature, performing feature extraction on a first frame and an adjacent frame and an optical flow between the first frame and the adjacent frame to obtain a second feature, and concatenating the first feature and the second feature to obtain a shallow layer feature; performing feature extraction and refinement on the shallow layer feature to obtain a plurality of output first features and a plurality of output second features; performing feature decoding on the plurality of output second features, and concatenating decoded features along channel dimensionality to obtain features; and performing weight distribution on the features to obtain final features, and restoring an image. The present invention can effectively help to improve image quality.
    Type: Grant
    Filed: January 7, 2021
    Date of Patent: January 21, 2025
    Assignee: SOOCHOW UNIVERSITY
    Inventors: Jianling Hu, Lihang Gao, Dong Liao, Jianfeng Yang, Honglong Cao
  • Publication number: 20250023007
    Abstract: The disclosure provides a light emitting device including a plurality of light emitting units and a plurality of wire bonding layers, each light emitting unit includes a first electrode and second electrode, the first electrode and the second electrode are spaced apart from each other, and the electrical properties of the first electrode and the second electrode are different. Multiple light emitting units are electrically connected to each other through multiple wire bonding layers, in which the spacing between two adjacent light emitting units is 0.5 ?m to 50 ?m, and the length of each wire bonding layer projected onto the light emitting unit is greater than or equal to 150 ?m.
    Type: Application
    Filed: September 27, 2024
    Publication date: January 16, 2025
    Applicant: LUMINUS (XIAMEN) CO., LTD
    Inventors: Xiaoqiang ZENG, Jianfeng YANG, Shaohua HUANG
  • Patent number: 12199217
    Abstract: A light-emitting chip includes a light-emitting unit, first and second electrode units. The light-emitting unit includes first and second conductivity type semiconductor layers and an active layer. The first electrode unit includes two first electrodes which are spaced apart from each other by a first distance, and which are electrically connected to the first conductivity type semiconductor layer. The second electrode unit includes two second electrodes electrically connected to the second conductivity type semiconductor layer. The first and second electrode units are spaced apart from each other by a second distance, and the first distance is greater than the second distance.
    Type: Grant
    Filed: January 4, 2022
    Date of Patent: January 14, 2025
    Assignee: LUMINUS (XIAMEN) CO., LTD.
    Inventors: Xiaoqiang Zeng, Kunte Lin, Jianfeng Yang, Kaiqing Xu, Shao-Hua Huang
  • Publication number: 20240386339
    Abstract: Disclosed are an accelerated test data analysis method and apparatus based on a grey forecast model, a device.
    Type: Application
    Filed: February 26, 2024
    Publication date: November 21, 2024
    Applicant: China Electronic Product Reliability and Environmoental Testing Research Institute
    Inventors: Guangze Pan, Dan Li, Bochen Chen, Lijun Sun, Yuanhang Wang, Wenwei Liu, Jianfeng Yang, Xiaojian Ding
  • Publication number: 20240378646
    Abstract: The present disclosure discloses a method and apparatus for estimating product lifetime based on a multi-stress accelerated test, and a device. This method can be applied in the field of data processing technologies, specifically including: determining, in response to a lifetime estimation request for a target product, a target characteristic lifetime of the target product based on a target stress condition for the target product and correspondence relationships between candidate stress conditions and candidate characteristic lifetimes; and determining, based on an optimal lifetime model for the type to which the target product belongs and the target characteristic lifetime, a target average life of the target product.
    Type: Application
    Filed: April 8, 2024
    Publication date: November 14, 2024
    Applicant: CHINA ELECTRONIC PRODUCT RELIABILITY AND ENVIROMENTAL TESTING RESEARCH INSTITUTE
    Inventors: Guangze PAN, Dan Li, Bochen Chen, Lijun Sun, Yuanhang Wang, Wenwei Liu, Jianfeng Yang, Xiaojian Ding
  • Publication number: 20240378130
    Abstract: A performance degradation-based product reliability weak link evaluation method includes: acquiring a performance degradation parameter of each component of a to-be-evaluated product corresponding to each test time point; evaluating the performance degradation parameter of each component corresponding to each test time point through a fault time evaluation model, to obtain a pre-fault operating duration of each component; evaluating the pre-fault operating duration of each component through a confidence-based unreliability evaluation method, to obtain an unreliability evaluation result of each component; generating at least one component service life distribution model corresponding to each component according to the unreliability evaluation result, and selecting a corresponding target component service life distribution model; and evaluating mean time between failures corresponding to each component according to the target component service life distribution model, and selecting a reliability weak link of th
    Type: Application
    Filed: March 11, 2024
    Publication date: November 14, 2024
    Inventors: Guangze PAN, Dan Li, Bochen Chen, Lijun Sun, Qian Li, Yuanhang Wang, Wenwei Liu, Jianfeng Yang, Xiaojian Ding
  • Patent number: 12124248
    Abstract: The present disclosure relates to a method and an apparatus for processing accelerated test data based on multiple performance degradation, and a device.
    Type: Grant
    Filed: April 3, 2024
    Date of Patent: October 22, 2024
    Assignee: CHINA ELECTRONIC PRODUCT RELIABILITY AND ENVIRONMENTAL TESTING RESEARCH INSTITUTE
    Inventors: Guangze Pan, Dan Li, Bochen Chen, Lijun Sun, Yuanhang Wang, Wenwei Liu, Jianfeng Yang, Xiaojian Ding
  • Patent number: 12127172
    Abstract: The present disclosure provides a periodic time slot scheduling method for a wireless network. The method includes: connecting a plurality of nodes by using a wireless network; constructing time slot parameter sets of nodes in the wireless network and an interval array between time slots of each of the nodes; calculating an acceptable total time interval of each of the nodes in the wireless network, selecting a node with a minimum acceptable total time interval in the wireless network as a time slot allocation node, allocating a time slot for each time slot request of the time slot allocation node, and allocating a time slot for each time slot request of a remaining node except the time slot allocation node in the wireless network; and detecting and determining a delay of time slot allocation.
    Type: Grant
    Filed: July 6, 2022
    Date of Patent: October 22, 2024
    Assignee: WUHAN UNIVERSITY
    Inventors: Jianfeng Yang, Chengcheng Guo
  • Patent number: 12119426
    Abstract: A light emitting device includes at least one light emitting unit that includes an insulating layer, a first electrically conductive layer, and a semiconductor layer structure having at least one recess. The first electrically conductive layer and the insulating layer extend into the recess. A contact area between a conductive protrusion portion of the first electrically conductive layer and a first-type semiconductor layer of the semiconductor layer structure is larger than 1.5% of an area of a bottom surface of the first-type semiconductor layer. A method for producing the light emitting device is also disclosed.
    Type: Grant
    Filed: April 8, 2021
    Date of Patent: October 15, 2024
    Assignee: QUANZHOU SAN'AN SEMICONDUCTOR TECHNOLOGY CO., LTD.
    Inventors: Shaohua Huang, Xiaoqiang Zeng, Canyuan Zhang, Jianfeng Yang
  • Publication number: 20240338270
    Abstract: The present disclosure relates to a method and an apparatus for reliability evaluation based on multiple performance degradation, a computer device, a storage medium, and a computer program product. The method includes: for each of the multiple performances of a target product, obtaining a plurality of candidate functions that the performance possibly follows, determining a target function that satisfies a preset selection condition from the plurality of candidate functions, and determining a reliability function corresponding to the performance based on the target function; determining coupling relation information between the multiple performances of the target product, and obtaining redundancy information of the multiple performances of the target product; and performing a reliability evaluation on the target product based on the coupling relation information, the redundancy information, and the reliability function of each performance.
    Type: Application
    Filed: February 29, 2024
    Publication date: October 10, 2024
    Inventors: Guangze Pan, Dan Li, Bochen Chen, Lijun Sun, Yuanhang Wang, Wenwei Liu, Jianfeng Yang, Xiaojian Ding
  • Publication number: 20240338016
    Abstract: The present disclosure relates to a method and an apparatus for processing accelerated test data based on multiple performance degradation, and a device.
    Type: Application
    Filed: April 3, 2024
    Publication date: October 10, 2024
    Applicant: CHINA ELECTRONIC PRODUCT RELIABILITY AND ENVIRONMENTAL TESTING RESEARCH INSTITUTE
    Inventors: Guangze PAN, Dan LI, Bochen CHEN, Lijun SUN, Yuanhang WANG, Wenwei LIU, Jianfeng YANG, Xiaojian DING