Abstract: A counterweight of washing machine, a washing machine and a counterweighting method for the washing machine relates to the technical field of washing machines. The counterweight of washing machine includes at least one counterweight cavity and at least one pressured water structure; a water entering port for connecting a water entering pipeline and a water draining port for connecting a water draining pipeline are formed on a wall of each of the at least one counterweight cavity; the at least one water pressurizing structure is disposed in each of the at least one counterweight cavity, and is configured to enable water entering each of the at least one counterweight cavity to be in an air-free sealed cavity. The counterweight of washing machine is mainly configured to reduce vibration and nose of the washing machine in work, and reduce the production and transportation cost of the washing machine.

Abstract: A counterweight of washing machine, a washing machine and a counterweighting method for the washing machine relates to the technical field of washing machines. The technical solutions mainly adopted are as follows: the counterweight of washing machine includes at least one counterweight cavity and at least one pressured water structure; a water entering port for connecting a water entering pipeline and a water draining port for connecting a water draining pipeline are formed on a wall of each of the at least one counterweight cavity; the at least one water pressurizing structure is disposed in each of the at least one counterweight cavity, and is configured to enable water entering each of the at least one counterweight cavity to be in an air-free sealed cavity; the counterweight of washing machine is configured to be fixed on a water containing drum of the washing machine; and the washing machine comprises the counterweight of washing machine.

Abstract: A phase-inverted clock generation circuit is provided, where sources of a first PMOS and a second PMOS are connected to a power source, drains of the first PMOS and the second PMOS are connected to a source of a third PMOS, and a drain of the third PMOS is connected to a drain of a third NMOS; and the drain of the third PMOS is connected to a drain of a second NMOS, a source of the second NMOS is connected to a drain of a first NMOS, and a source of the first NMOS and a source of the third NMOS.

Abstract: A phase-inverted clock generation circuit is provided, where sources of a first PMOS and a second PMOS are connected to a power source, drains of the first PMOS and the second PMOS are connected to a source of a third PMOS, and a drain of the third PMOS is connected to a drain of a third NMOS; and the drain of the third PMOS is connected to a drain of a second NMOS, a source of the second NMOS is connected to a drain of a first NMOS, and a source of the first NMOS and a source of the third NMOS.