Patents by Inventor JIANG JUNMIN

JIANG JUNMIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Multi-stage switched capacitor converter and variable conversion ratio switched capacitor converter
    Patent number: 10103621
    Abstract: A system comprising: a switched capacitor circuit comprising a plurality of voltage divider circuit stages including a first voltage divider circuit stage coupled to a second voltage divider circuit stage; and a controller configured to supply a clock signal to the first voltage divider circuit stage to provide a first voltage on an output node of the first voltage divider circuit stage during a first half cycle of the clock signal, and a second voltage on said output node during a second half cycle of the clock signal. The second voltage divider circuit stage is configured to charge to an input voltage during a half cycle of the clock signal, and the controller is configured to synchronize charging of the second voltage divider circuit stage to a selected one of (i) the first half cycle of the clock signal, wherein the first voltage is supplied as said input voltage, and (ii) the second half cycle of the clock signal, wherein the second voltage is supplied as said input voltage.
    Type: Grant
    Filed: August 10, 2015
    Date of Patent: October 16, 2018
    Assignee: PHILIPS LIGHTING HOLDING B.V.
    Inventors: Jiang Junmin, Jie Fu, Shu Xu
  • SWITCHED CAPACITOR CONVERTER
    Publication number: 20170264192
    Abstract: A system comprising: a switched capacitor circuit comprising a plurality of voltage divider circuit stages including a first voltage divider circuit stage coupled to a second voltage divider circuit stage; and a controller configured to supply a clock signal to the first voltage divider circuit stage to provide a first voltage on an output node of the first voltage divider circuit stage during a first half cycle of the clock signal, and a second voltage on said output node during a second half cycle of the clock signal. The second voltage divider circuit stage is configured to charge to an input voltage during a half cycle of the clock signal, and the controller is configured to synchronize charging of the second voltage divider circuit stage to a selected one of (i) the first half cycle of the clock signal, wherein the first voltage is supplied as said input voltage, and (ii) the second half cycle of the clock signal, wherein the second voltage is supplied as said input voltage.
    Type: Application
    Filed: August 10, 2015
    Publication date: September 14, 2017
    Inventors: JIANG JUNMIN, JIE FU, SHU XU