Abstract: A method and a corresponding system for characterizing the performance of a clock and data recovery circuit in a digital transceiver is presented. The method comprises phase modulating a jitter-free data signal by a testing signal having added data jitter and measuring the time the clock and data recovery system takes to achieve bit lock of a phase modulated signal. Data uncorrelated timing jitter corresponding to a user defined probability distribution is included in the jitter testing signal. Utilization of a variable probability distribution in generating data uncorrelated timing jitter, as provided by the present invention, allows for greater flexibility and accuracy in clock and data recovery circuit testing and characterization.

Abstract: Consistent with the present invention, there is provided a circuit for extracting a common mode voltage of an input signal. The device may include an operational amplifier having an output, at least one negative input and at least one positive input, a first transistor, and a second transistor. A terminal of the first transistor may be coupled to the output of the operational amplifier. A terminal of the second transistor may be coupled to a terminal of the first transistor and the at least one positive input of the operational amplifier to create a negative feedback loop. The device may further include a common mode output, wherein the negative feedback loop extracts the common mode voltage of the input signal, the common mode voltage of the input signal being output at the common mode output. The device consistent with the present invention may provide the common mode voltage of the input signal without using any resistors, and while only occupying a small die area.

Abstract: A method and a corresponding system for characterizing the performance of a clock and data recovery circuit in a digital transceiver is presented. The method comprises phase modulating a jitter-free data signal by a testing signal having added data jitter and measuring the time the clock and data recovery system takes to achieve bit lock of a phase modulated signal. Data uncorrelated timing jitter corresponding to a user defined probability distribution is included in the jitter testing signal. Utilization of a variable probability distribution in generating data uncorrelated timing jitter, as provided by the present invention, allows for greater flexibility and accuracy in clock and data recovery circuit testing and characterization.

Abstract: Consistent with the present invention, there is provided a circuit for extracting a common mode voltage of an input signal. The device may include an operational amplifier having an output, at least one negative input and at least one positive input, a first transistor, and a second transistor. A terminal of the first transistor may be coupled to the output of the operational amplifier. A terminal of the second transistor may be coupled to a terminal of the first transistor and the at least one positive input of the operational amplifier to create a negative feedback loop. The device may further include a common mode output, wherein the negative feedback loop extracts the common mode voltage of the input signal, the common mode voltage of the input signal being output at the common mode output. The device consistent with the present invention may provide the common mode voltage of the input signal without using any resistors, and while only occupying a small die area.