Abstract: An anti-cavitation damping composite metal structure for a flow passage component and a preparation method thereof are provided. The preparation method includes: cladding a gradient functional material layer by layer on a substrate of a flow passage component; forming periodic structures on a surface of each layer of the gradient functional material through etching by an ultrafast laser to absorb a part of an impact load energy caused by cavitation of the flow passage component, where the layers of the gradient functional material form a gradient coating with a toughness increasing layer by layer and a hardness decreasing layer by layer from bottom to top; and forming nano twins on a surface layer by a laser shock peening technique, and implanting a residual compressive stress to further improve anti-cavitation resistance of a surface.

Abstract: The present disclosure belongs to the technical field of wastewater treatment, and discloses an electrochemical nitrogen and phosphorus removal device and a method.

Abstract: The present invention provides a keratin BD-3, a nucleic acid molecule encoding same, an expression vector, a host cell, a preparation method therefor, and a pharmaceutical composition contained the keratin BD-3. The keratin BD-3 can be used in the preparation of medicament for antipyretic, analgesic, antitussive, expectorant, anticonvulsant, antiepileptic, anti-hypertension, anti-inflammatory, and antiviral.

Abstract: The invention discloses a method for preparing an anticorrosive surface layer of a metal material in a marine environment by laser, which belongs to the technical field of laser processing. First, the laser cladding method is used to prepare a cladding surface layer on the surface of the metal material that is not easy to undergo chemical substitution reaction with the chlorides (NaCl, MgCl2 , CaCl2 etc.) in the seawater. Then, on the surface of the cladding surface layer, ultrafast laser processing is used to form a surface layer with a wetting angle (and water) greater than 90 degrees and with hydrophobic characteristics.

Abstract: A system and method for determining over-voltage and under-voltage thresholds in a voltage regulator are disclosed herein. A voltage regulator includes an over-voltage detector and an under-voltage detector that determine whether the voltage regulator's regulated output voltage is above or below predetermined over-voltage and under-voltage thresholds respectively. The over-voltage detector connects to an output port that provides a signal indicating that the regulated voltage output is greater than the predetermined over-voltage threshold and not lower than the predetermined under-voltage threshold. The under-voltage detector connects to an output port that provides a signal indicating that the regulated voltage output is lower than the predetermined under-voltage threshold and not greater than the predetermined over-voltage threshold. The voltage regulator also includes an input port that provides a test signal for testing the voltage levels of the over-voltage threshold and the under-voltage threshold.

Abstract: A method for testing a semiconductor device is included where sleep mode commands associated with the semiconductor device are generated. The semiconductor device includes logic blocks, where a sleep mode command sets a logic block in a sleep mode. A sleep mode sequence associated with the logic blocks of the semiconductor device is determined. The sleep mode commands are executed according to the sleep mode sequence by applying the sleep mode commands to the logic blocks. A quiescent current corresponding to the semiconductor device is measured in order to test the semiconductor device.

Abstract: A method for testing a semiconductor device is included where sleep mode commands associated with the semiconductor device are generated. The semiconductor device includes logic blocks, where a sleep mode command sets a logic block in a sleep mode. A sleep mode sequence associated with the logic blocks of the semiconductor device is determined. The sleep mode commands are executed according to the sleep mode sequence by applying the sleep mode commands to the logic blocks. A quiescent current corresponding to the semiconductor device is measured in order to test the semiconductor device.