Abstract: A system and method for determining over-voltage and under-voltage thresholds in a voltage regulator are disclosed herein. A voltage regulator includes an over-voltage detector and an under-voltage detector that determine whether the voltage regulator's regulated output voltage is above or below predetermined over-voltage and under-voltage thresholds respectively. The over-voltage detector connects to an output port that provides a signal indicating that the regulated voltage output is greater than the predetermined over-voltage threshold and not lower than the predetermined under-voltage threshold. The under-voltage detector connects to an output port that provides a signal indicating that the regulated voltage output is lower than the predetermined under-voltage threshold and not greater than the predetermined over-voltage threshold. The voltage regulator also includes an input port that provides a test signal for testing the voltage levels of the over-voltage threshold and the under-voltage threshold.

Abstract: A method for testing a semiconductor device is included where sleep mode commands associated with the semiconductor device are generated. The semiconductor device includes logic blocks, where a sleep mode command sets a logic block in a sleep mode. A sleep mode sequence associated with the logic blocks of the semiconductor device is determined. The sleep mode commands are executed according to the sleep mode sequence by applying the sleep mode commands to the logic blocks. A quiescent current corresponding to the semiconductor device is measured in order to test the semiconductor device.

Abstract: A method for testing a semiconductor device is included where sleep mode commands associated with the semiconductor device are generated. The semiconductor device includes logic blocks, where a sleep mode command sets a logic block in a sleep mode. A sleep mode sequence associated with the logic blocks of the semiconductor device is determined. The sleep mode commands are executed according to the sleep mode sequence by applying the sleep mode commands to the logic blocks. A quiescent current corresponding to the semiconductor device is measured in order to test the semiconductor device.