Abstract: The present invention discloses an apparatus for combining partially defected synchronous dynamic random access memories. By selecting each memory chip with corresponding workable blocks, the partially defected SDRAMs can be combined as a workable device which can be programmed and operated in the same way as a defect-free chip. The apparatus for combining partially defected synchronous dynamic random access memory chips of the present invention includes a workable block selecting circuit and a chip selecting circuit. The workable block selecting circuit is responsive to a reference signal for selecting workable blocks of the synchronous dynamic random access memories. The chip selecting circuit is responsive to a chip selecting signal and the reference signal for selecting a chip from the synchronous dynamic random access memory chips.

Abstract: A programmable I/O remapper for mapping partially defective memory devices to a memory data bus of an electronic system is disclosed. The remapper apparatus includes at least one defective memory device responsive to control signals and address signals of the electronic system. A switch circuit including several electrical type switches is used for generating mapped data bits, which are coupled the memory data bus of the electronic system. A data register is used for storing enable signals to control the switches of the switch circuit.

Abstract: An apparatus for accessing an extended data output dynamic random access memory (EDO DRAM) is disclosed. A conventional fast page mode (FPM) DRAM is converted by the present invention to conform to an EDO DRAM. The present invention comprises a conventional FPM DRAM, a read-cycle generating circuit for generating a signal that defines a read cycle, a flip-flop for latching data signals from the FPM DRAM, an output control circuit for generating a control signal to control a data switch that will pass the latched data signals. The data signals come directly from the FPM DRAM and the latched data signals come from the data switch are combined to form extended data signals coupled to a system data bus.

Abstract: An apparatus and method for bit defect compensation is disclosed which comprises a tag address means for storing addresses of defective bits of a DRAM; a compensation data means for storing replacing bits utilized to replace the defective bits; a control circuit that provides logic and timing controls for compensation actions; and a comparator that provides comparison function between DRAM access address and addresses stored in the tag address means, and generates a compensation address to access the replacing bits in the compensation data means when necessary. The present invention provides an improved apparatus and method for compensating for the problem of bit defect, and improving the traditional fail bit memory scheme.