Patents by Inventor Jiangfeng Wu
Jiangfeng Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7583179Abstract: A transceiver for a RFID reader and a transceiver for a RFID transponder (tag) allow communication between the two devices. The RFID reader utilizes an analog front end and a digital backend. In the receiver portion of the transceiver, the front end of the RFID reader uses a pair of down-conversion mixers to demodulate a received signal into in-phase (I) and quadrature (Q) components and analog-to-digital converters (ADC) digitize the signal. A digital signal processor (DSP) in the back end processes the digital signal and uses a matched filter for data detection. The RFID tag receives an inductively coupled signal from the reader and the receiver portion of the tag uses a pulse/level detector that employs an analog comparator and a sample and hold circuit to detect the received signal. A digital decoder/controller is used to decode the incoming data and to establish a sampling clock for the pulse/level detector.Type: GrantFiled: June 16, 2005Date of Patent: September 1, 2009Assignee: Broadcom CorporationInventors: Jiangfeng Wu, Donald Edward Major
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Publication number: 20090174816Abstract: Aspects of a method and system for detection of video connections are provided. In this regard, a pulse of current may be applied to a video interface and a voltage differential resulting from the applied current pulse may be measured to determine whether the video interface is connected to a video device. The current pulse may be a Hsync pulse of a video signal which may occur during a vertical blanking time of the video signal. A voltage differential resulting from each of a plurality of Hsync pulses occurring over one or more frames of said video signals may be measured. The current pulse may be a pulse in a pulse train. A voltage differential resulting from each of a plurality of pulses in a pulse train occurring over a period of time may be measured.Type: ApplicationFiled: May 9, 2008Publication date: July 9, 2009Inventors: Tim Hellman, Jiangfeng Wu, Hans Eberhart
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Publication number: 20090115384Abstract: Apparatuses, methods, and systems for effective power management distribution are provided. In an embodiment, a system for providing power to a circuit block comprises a power management unit (PMU) configured on a first substrate and an integrated circuit (IC) configured on a second substrate. The PMU includes a first regulator configured to step down an input voltage and output a first regulated voltage. The IC includes the circuit block and a second regulator configured to receive the first regulated voltage and output a second regulated voltage. The second power regulated voltage provides power to the circuit block. The first regulator is more efficient than the second regulator.Type: ApplicationFiled: October 29, 2008Publication date: May 7, 2009Applicant: Broadcom CorporationInventors: Ardie VENES, Tianwei Li, Jiangfeng Wu, Pieter Vorenkamp
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Publication number: 20080101592Abstract: A line driver comprises a driving amplifier receiving an input of the line driver, a current sense resistor connected between the driving amplifier output and the line driver output, and a feedback amplifier sensing the voltage across the current sense resistor and providing a corresponding feedback voltage that is proportional to the output current to the driving amplifier, thereby determining an output impedance at the line driver output. Precise output impedance can be realized by using a high precision resistor as the current sense resistor, and using resistive feedback amplifiers with accurate gains as the driving and feedback amplifiers. The resistance of the current sense resistor can be substantially less than the line driver output impedance, and the driving amplifier output voltage swing can be substantially less than twice the line driver output voltage swing.Type: ApplicationFiled: October 30, 2006Publication date: May 1, 2008Inventors: Jiangfeng Wu, Tianwei Li, Arnoldus Venes
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Publication number: 20060238301Abstract: A transceiver for a RFID reader and a transceiver for a RFID transponder (tag) allow communication between the two devices. The RFID reader utilizes an analog front end and a digital backend. In the receiver portion of the transceiver, the front end of the RFID reader uses a pair of down-conversion mixers to demodulate a received signal into in-phase (I) and quadrature (Q) components and analog-to-digital converters (ADC) digitize the signal. A digital signal processor (DSP) in the back end processes the digital signal and uses a matched filter for data detection. The RFID tag receives an inductively coupled signal from the reader and the receiver portion of the tag uses a pulse/level detector that employs an analog comparator and a sample and hold circuit to detect the received signal. A digital decoder/controller is used to decode the incoming data and to establish a sampling clock for the pulse/level detector.Type: ApplicationFiled: June 16, 2005Publication date: October 26, 2006Inventors: Jiangfeng Wu, Donald Major
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Publication number: 20060186995Abstract: A transceiver for a RFID reader and a transceiver for a RFID transponder (tag) allow communication between the two devices. The RFID reader utilizes an analog front end and a digital backend. In the receiver portion of the transceiver, the front end of the RFID reader uses a pair of down-conversion mixers to demodulate a received signal into in-phase (I) and quadrature (Q) components and analog-to-digital converters (ADC) digitize the signal. A digital signal processor (DSP) in the back end processes the digital signal and uses a matched filter for data detection. The RFID tag receives an inductively coupled signal from the reader and the receiver portion of the tag uses a pulse/level detector that employs an analog comparator and a sample and hold circuit to detect the received signal. A digital decoder/controller is used to decode the incoming data and to establish a sampling clock for the pulse/level detector.Type: ApplicationFiled: June 16, 2005Publication date: August 24, 2006Inventors: Jiangfeng Wu, Donald Major
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Patent number: 7085240Abstract: Disclosed are systems and methods which proactively determine particular access terminals which are compatible for simultaneous communication at a high data rate and preferred embodiments provide scheduling of simultaneous communications such that data communication is optimized. Preferred embodiments of the present invention utilize a multiple element antenna array, and associated array response vectors associated with narrow antenna beam forming techniques, (adaptive array antennas) to identify compatible access terminals, such as by calculating a correlation between particular access terminals and, preferably utilizing a predetermined correlation threshold, identifying suitably uncorrelated access terminals. Using such information embodiments of the present invention may determine which particular access terminals may be controlled to transmit at a high data rate at a same time. Embodiments of the present invention are operable with respect to the forward and/or reverse links.Type: GrantFiled: June 5, 2001Date of Patent: August 1, 2006Assignee: Kathrein-Werke KGInventors: Jiangfeng Wu, Piu Bill Wong, Shimon B. Scherzer
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Publication number: 20060114345Abstract: There is provided a circuit comprising a plurality of pixels arranged in rows and columns, a charge pump having a first input voltage and a second input voltage and having at least one output, at least one reset driver operatively connected to each row of the pixels, wherein the at least output of the charge pump provides a first reset voltage to at least one row of pixels at a first time and provides a second reset voltage to at least one row of other pixels at a second time. The charge pump may include a capacitor selectively connected to the first input voltage and the second input voltage, whereon the capacitor accumulates a boosted voltage.Type: ApplicationFiled: December 1, 2004Publication date: June 1, 2006Inventors: Jiangfeng Wu, Jiafu Luo
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Patent number: 7029788Abstract: A 9V rechargeable battery comprising a plurality of column cells connected in series and enclosed by a container and a cover with a negative terminal and a positive terminal. Said container (1) further comprises a pair of lateral sidewalls formed with openings and another pair of lateral sidewalls formed with recesses so as to receive said cells snugly.Type: GrantFiled: August 23, 2002Date of Patent: April 18, 2006Assignee: Shenzhen Likexing Battery Co., Ltd.Inventors: Jianbo Yu, Ping Zhang, Jiangfeng Wu, Xuefeng Gao
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Patent number: 7016649Abstract: The present invention utilizes adaptive antenna arrays at a base station to increase the forward link capacity of mobile data systems. One or more simultaneous forward link beams are formed and are switched (or hopped) in a time division manner among subscribers. The beam hopping sequence is randomized by varying the time slot and/or carrier frequency of each subscriber. In space-time hopping, the position within a frame of the time slot for each subscriber is varied in a pseudo random sequence. In space-frequency hopping, the carrier frequency for each frame is varied in a pseudo random sequence. The pseudo random beam hopping sequence provides a gain due to interference diversity in addition to the antenna array gain. Forward link beam forming algorithms use space-time or space-frequency hopping to increase the capacity of mobile data systems.Type: GrantFiled: March 9, 2001Date of Patent: March 21, 2006Assignee: Kathrein-Werke KGInventors: Ravi Narasimhan, Piu Bill Wong, Shimon B. Scherzer, Jiangfeng Wu
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Patent number: 6697644Abstract: The invention provides optimization of communication links by using a control loop with a relatively long time constant and adjusting particular communication links based upon feedback from a virtual communication unit associated with a communication link. A preferred embodiment of the invention optimizes wireless links in a point to multipoint system, such as a cellular communication system, by dividing a service area into segments and adjusting an antenna beam associated with a segment when a mobile unit is operable therein. This preferred embodiment results in convergence upon an optimized communication link over time and is suitable for use even with highly mobile systems. Preferred embodiments of the invention provide control loops for location or segment optimization as well as for individual optimization.Type: GrantFiled: February 6, 2001Date of Patent: February 24, 2004Assignee: Kathrein-Werke KGInventors: Shimon B. Scherzer, Piu Bill Wong, Jiangfeng Wu, Alexander V. Tesler
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Patent number: 6614273Abstract: An ultra-fast drive circuit (40) providing a rail-to-rail drive voltage at an output node (N1). A pair of bipolar output transistors (Q3, Q4) are selectively driven via a FET drive circuit (42), and by a control circuit (44) to achieve a rail-to-rail output voltage (Vcc−Vee) that is very fast. The drive FETs comprise three serially connected FETs (M5, M6, M7) whereby the middle FET (M6) is the control FET effecting the control of the output transistors (Q3, Q4). The other two FETs (M5, M7) are always in the on state and complete either the pull-up or pull-down of the voltage at the output node (N1), depending on the state of the middle FET (M6). The control FETs (44) provide two output control signals (46, 48) to the output transistors (Q3, Q4), with the control line (48) controlling the state of the middle switching FET (M6).Type: GrantFiled: January 30, 2001Date of Patent: September 2, 2003Assignee: Texas Instruments IncorporatedInventors: Patrick Teterud, Jiangfeng Wu, Thomas Van Eaton
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Publication number: 20030054238Abstract: A 9V rechargeable battery comprising a plurality of column cells connected in series and enclosed by a container and a cover with a negative terminal and a positive terminal. Said container (1) further comprises a pair of lateral sidewalls formed with openings and another pair of lateral sidewalls formed with recesses so as to receive said cells snugly.Type: ApplicationFiled: August 23, 2002Publication date: March 20, 2003Inventors: Jianbo Yu, Ping Zhang, Jiangfeng Wu, Xuefeng Gao
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Publication number: 20030016737Abstract: Disclosed are systems and methods which proactively determine particular access terminals which are compatible for simultaneous communication at a high data rate and preferred embodiments provide scheduling of simultaneous communications such that data communication is optimized. Preferred embodiments of the present invention utilize a multiple element antenna array, and associated array response vectors associated with narrow antenna beam forming techniques, (adaptive array antennas) to identify compatible access terminals, such as by calculating a correlation between particular access terminals and, preferably utilizing a predetermined correlation threshold, identifying suitably uncorrelated access terminals. Using such information embodiments of the present invention may determine which particular access terminals may be controlled to transmit at a high data rate at a same time. Embodiments of the present invention are operable with respect to the forward and/or reverse links.Type: ApplicationFiled: June 5, 2001Publication date: January 23, 2003Inventors: Jiangfeng Wu, Piu Bill Wong, Shimon B. Scherzer
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Patent number: 6510190Abstract: The present invention relates to a method and an apparatus for compensating a signal that has experienced fading distortion in a communication channel. The signal that can be a TDMA (Time Division Multiple Access) signal includes slots that carry data symbols. Non-uniformly spaced pilot symbols are also embedded in the slot structure. The receiver separates the incoming symbols stream in two parts namely a pilot symbols stream and data symbols stream. Since the transmitted pilot symbols are known, an estimate of the channel distortion on the pilot symbols locations can be computed. This estimate is then interpolated to provide an estimate of the fading distortion at the data symbols locations, thus allowing to compensate accurately for the fading distortion in the channel.Type: GrantFiled: December 17, 1998Date of Patent: January 21, 2003Assignee: Nortel Networks LimitedInventors: Jiangfeng Wu, Jan Corneliu Olivier, Chengshan Xiao
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Publication number: 20020146983Abstract: The invention provides optimization of communication links by using a control loop with a relatively long time constant and adjusting particular communication links based upon feedback from a virtual communication unit associated with a communication link. A preferred embodiment of the invention optimizes wireless links in a point to multipoint system, such as a cellular communication system, by dividing a service area into segments and adjusting an antenna beam associated with a segment when a mobile unit is operable therein. This preferred embodiment results in convergence upon an optimized communication link over time and is suitable for use even with highly mobile systems. Preferred embodiments of the invention provide control loops for location or segment optimization as well as for individual optimization.Type: ApplicationFiled: February 6, 2001Publication date: October 10, 2002Inventors: Shimon B. Scherzer, Piu Bill Wong, Jiangfeng Wu, Alexander V. Tesler
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Publication number: 20020101267Abstract: An ultra-fast drive circuit (40) providing a rail-to-rail drive voltage at an output node (N1). A pair of bipolar output transistors (Q3, Q4) are selectively driven via a FET drive circuit (42), and by a control circuit (44) to achieve a rail-to-rail output voltage (Vcc-Vee) that is very fast. The drive FETs comprise three serially connected FETs (M5, M6, M7) whereby the middle FET (M6) is the control FET effecting the control of the output transistors (Q3, Q4). The other two FETs (M5, M7) are always in the on state and complete either the pull-up or pull-down of the voltage at the output node (N1), depending on the state of the middle FET (M6). The control FETs (44) provide two output control signals (46, 48) to the output transistors (Q3, Q4), with the control line (48) controlling the state of the middle switching FET (M6).Type: ApplicationFiled: January 30, 2001Publication date: August 1, 2002Inventors: Patrick Teterud, Jiangfeng Wu, Thomas Van Eaton