Patents by Inventor Jianghua Wan

Jianghua Wan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11919936
    Abstract: Provided are a TEV protease variant, a fusion protein thereof, a preparation method therefor and the use thereof. Provided are a TEV protease variant with unique properties obtained by screening and a fusion protein thereof. The TEV protease variant has a low enzyme cleavage activity during expression in hosts, and preferably has a lower enzyme cleavage activity compared to an S219V variant having an amino acid sequence as shown in SEQ ID NO: 10. The enzyme cleavage site of the TEV protease variant is selected from EXXYXQG/S/H, wherein X is any amino acid residue, and the enzyme cleavage site is preferably selected from SEQ ID NO: 7 and 8. Fusion expression using the TEV protease variant of the present invention and a polypeptide can be used for preparing a polypeptide quickly and efficiently, thereby solving the problems currently present in the process of the recombinant production of a polypeptide.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: March 5, 2024
    Assignee: SHANGRAO CONCORD PHARMACEUTICAL CO., LTD.
    Inventors: Rikui Liu, Xiaolong Zou, Jianghua Wan
  • Patent number: 11852666
    Abstract: Disclosed are circuit and method for width measurement of digital pulse signals. The circuit comprises: a sample clock, used to drive all registers in the circuit; an edge detection and interrupt control unit, used to detect a rising edge and a falling edge of a pulse signal on an input pin Input to control signal collection; an integer encoding unit comprising a counter and registers and used to measure an integer part ? of the width of a high or low level on the input pin Input with one period 1/f of the sample clock as a reference unit; a signal capture chain, used to sample an output level of each delay cell DLL; a decimal encoding unit, used to find out and record the propagation position of the pulse edge on the signal capture chain; and a calibration control unit, used to perform calibration.
    Type: Grant
    Filed: April 25, 2021
    Date of Patent: December 26, 2023
    Assignee: HUNAN GREAT-LEO MICROELECTRONICS CO., LTD.
    Inventors: Hu Chen, Ye Xu, Jianghua Wan
  • Patent number: 11695396
    Abstract: A circuit, for generating ultrahigh-precision digital pulse signals comprises: a pulse edge control circuit used for delaying a signal on an input pin and accurately controlling positions of a rising edge and a falling edge of the pulse signal to accurately control the width of pulses and generate ultrahigh-precision pulses; a static calibration circuit used for calculating step size information representing the relationship between a work clock period of a system and a delay of delay cells in the pulse edge control circuit when the system is powered on to work, and storing the step size information, wherein the step size information is the number of delay cells through which the signal is propagated and passes within one system clock period; and a dynamic calibration circuit used for dynamically calculating step size information when a rising edge or a falling edge of each pulse in the input pin arrives.
    Type: Grant
    Filed: January 29, 2021
    Date of Patent: July 4, 2023
    Assignee: HUNAN GREAT-LEO MICROELECTRONICS CO., LTD.
    Inventors: Hu Chen, Ye Xu, Jianghua Wan
  • Publication number: 20220308102
    Abstract: Disclosed are circuit and method for width measurement of digital pulse signals. The circuit comprises: a sample clock, used to drive all registers in the circuit; an edge detection and interrupt control unit, used to detect a rising edge and a falling edge of a pulse signal on an input pin Input to control signal collection; an integer encoding unit comprising a counter and registers and used to measure an integer part ? of the width of a high or low level on the input pin Input with one period 1/f of the sample clock as a reference unit; a signal capture chain, used to sample an output level of each delay cell DLL; a decimal encoding unit, used to find out and record the propagation position of the pulse edge on the signal capture chain; and a calibration control unit, used to perform calibration.
    Type: Application
    Filed: April 25, 2021
    Publication date: September 29, 2022
    Applicant: HUNAN GREAT-LEO MICROELECTRONICS CO., LTD.
    Inventors: Hu CHEN, Ye XU, Jianghua WAN
  • Publication number: 20220173727
    Abstract: A circuit, for generating ultrahigh-precision digital pulse signals, comprises: a pulse edge control circuit used for delaying a signal on an input pin and accurately controlling positions of a rising edge and a falling edge of the pulse signal to accurately control the width of pulses and generate ultrahigh-precision pulses; a static calibration circuit used for calculating step size information representing the relationship between a work clock period of a system and a delay of delay cells in the pulse edge control circuit when the system is powered on to work, and storing the step size information, wherein the step size information is the number of delay cells through which the signal is propagated and passes within one system clock period; and a dynamic calibration circuit used for dynamically calculating step size information when a rising edge or a falling edge of each pulse in the input pin arrives.
    Type: Application
    Filed: January 29, 2021
    Publication date: June 2, 2022
    Applicant: HUNAN GREAT-LEO MICROELECTRONICS CO., LTD.
    Inventors: Hu CHEN, Ye XU, Jianghua WAN
  • Publication number: 20220056099
    Abstract: Provided are a TEV protease variant, a fusion protein thereof, a preparation method therefor and the use thereof. Provided are a TEV protease variant with unique properties obtained by screening and a fusion protein thereof. The TEV protease variant has a low enzyme cleavage activity during expression in hosts, and preferably has a lower enzyme cleavage activity compared to an S219V variant having an amino acid sequence as shown in SEQ ID NO: 10. The enzyme cleavage site of the TEV protease variant is selected from EXXYXQG/S/H, wherein X is any amino acid residue, and the enzyme cleavage site is preferably selected from SEQ ID NO: 7 and 8. Fusion expression using the TEV protease variant of the present invention and a polypeptide can be used for preparing a polypeptide quickly and efficiently, thereby solving the problems currently present in the process of the recombinant production of a polypeptide.
    Type: Application
    Filed: January 11, 2019
    Publication date: February 24, 2022
    Inventors: Rikui Liu, Xiaolong Zou, Jianghua Wan
  • Publication number: 20220025355
    Abstract: The present invention relates to a method for screening a protease variant and the obtained protease variant, and the protease variant has a special performance. The method for screening the protease variant comprises the following steps: (1) constructing a protease random mutation library, optimizing a protease random mutation virus library, and optimizing a protease random mutation phage library; (2) for the protease random mutation library, optimizing the protease random mutation virus library, and optimizing the protease random mutation phage library and screening a protease variant having weak protease enzyme-cutting activity in a host or a similar condition and having protease enzyme-cutting activity in an in vitro denaturation condition; and (3) the step of optionally characterizing the protease variant, wherein the protease optimizes TEV protease or enterokinase. The protease variant in the present invention facilitates industrial production of protein.
    Type: Application
    Filed: January 11, 2019
    Publication date: January 27, 2022
    Inventors: Rikui Liu, Xiaolong Zou, Jianghua Wan