Abstract: The present invention relates to a solvent-free polyurethane adhesive composition and the use thereof.

Abstract: Provided are a PCIe interrupt processing method and apparatus, a device and a non-transitory readable storage medium, relating to the technical field of computers. The PCIe interrupt processing method comprises: a currently generated internal interrupt signal is acquired; a PCIe interrupt type supported by a current FPGA is determined according to an interrupt vector signal output by a PCIe IP core, so as to determine a corresponding target interrupt processing mechanism according to the PCIe interrupt type; and the internal interrupt signal is processed by means of the target interrupt processing mechanism, and a processing result is input to the PCIe IP core, such that the PCIe IP core sends an interrupt message packet to a central processing unit on the basis of the processing result. The technical solution expands the compatibility of an FPGA with processor interrupts, facilitating the implementation of FPGA logic platform construction.

Abstract: A graph data processing method includes: acquiring target graph data to be processed; compiling statistics on the target graph data according to a first preset rule, so as to divide the target graph data into a plurality of graph data blocks and determine a boundary value and weight of each of the plurality of graph data blocks; and storing the boundary value and weight of each of the plurality of graph data blocks in a corresponding memory according to a second preset rule, so as to schedule the target graph data during a graph calculation process by use of the boundary values and the weights.

Abstract: Provided are a communication method and system for a distributed heterogeneous acceleration platform, a device and a medium. The method includes: after starting a collaborative acceleration task, determining, by a first target heterogeneous acceleration card in a distributed heterogeneous acceleration platform, a second target heterogeneous acceleration card from the distributed heterogeneous acceleration platform by querying an information table corresponding to the collaborative acceleration task; generating, by the first target heterogeneous acceleration card, a target data packet according to a predefined data packet format, and sending the target data packet to the second target heterogeneous acceleration card via a PCIE interface; and parsing, by the second target heterogeneous acceleration card, the target data packet according to the data packet format, and executing a corresponding read operation or write operation according to a parsing result, so as to complete the collaborative acceleration task.

Abstract: A far-end data migration device and method based on a FPGA cloud platform. The device includes a server, a switch, and a plurality of FPGA acceleration cards. The server transmits data to be accelerated to the FPGA acceleration cards by means of the switch. The FPGA acceleration cards are configured to perform a primary and/or secondary acceleration on the data, and are configured to migrate the accelerated data. The method includes: transmitting data to be accelerated to a FPGA acceleration card from a server by means of a switch; performing, by the FPGA acceleration card, a primary and/or secondary acceleration on the data to be accelerated; and migrating, by the FPGA acceleration card, the accelerated data.

Abstract: A method and apparatus for performing a power stress test on an FPGA acceleration card and a computer-readable storage medium. The method includes: dividing, according to a partial reconfiguration method, a hardware resource of an FPGA acceleration card into a static region serving as a hardware logic implementation region for performing a normal function test, and a dynamic PR region including a blank mode occupying no hardware resource and a power test mode for performing a power stress test, and burning FPGA firmware having a partial reconfiguration function to a flash memory; upon receiving a request for power stress test, configuring an operation mode of the dynamic PR region to be the power test mode, loading, to the dynamic PR region, a dynamic PR configuration file burned in the flash memory; and calling a power stress test module to execute the power stress test in the dynamic PR region.

Abstract: A graph data processing method includes: acquiring target graph data to be processed; compiling statistics on the target graph data according to a first preset rule, so as to divide the target graph data into a plurality of graph data blocks and determine a boundary value and weight of each of the plurality of graph data blocks; and storing the boundary value and weight of each of the plurality of graph data blocks in a corresponding memory according to a second preset rule, so as to schedule the target graph data during a graph calculation process by use of the boundary values and the weights.

Abstract: A method and apparatus for performing a power stress test on an FPGA acceleration card and a computer-readable storage medium. The method includes: dividing, according to a partial reconfiguration method, a hardware resource of an FPGA acceleration card into a static region serving as a hardware logic implementation region for performing a normal function test, and a dynamic PR region including a blank mode occupying no hardware resources and a power test mode for performing a power stress test, and burning FPGA firmware having a partial reconfiguration function to a flash memory; upon receiving a request for power stress test, configuring an operation mode of the dynamic PR region to be the power consumption test mode, loading, to the dynamic PR region, a dynamic PR configuration file burned in the flash memory; and calling a power stress test module to execute the power stress test in the dynamic PR region.

Abstract: Disclosed is an Avalon-to-Axi4 bus conversion method, including: in case that an Avalon bus is an Avalon_st bus, receiving Avalon_st bus data, performing a logical process on the received Avalon_st bus data, and then outputting corresponding Axi4_st bus data; and in case that the Avalon bus is an Avalon_mm bus, receiving a signal transmitted by each channel of the Avalon_mm bus, framing and storing the signal in asynchronous First Input First Output (FIFO), and in case that a device corresponding to an Axi4 bus is ready, reading the signal from the asynchronous FIFO, and outputting the signal to a corresponding channel of the Axi4 bus according to a timing relationship of the Axi4 bus.

Abstract: Provided is a material performance testing system under a fixed multi-field coupling effect in a hypergravity environment, including a hoisted sealed cabin, a bearing frame, a high-temperature furnace, a mechanical test device, and a buffer device. The bearing frame and the high-temperature furnace are fixedly mounted inside the hoisted sealed cabin. The bearing frame is covered on the high-temperature furnace. The buffer device is mounted at a bottom of the high-temperature furnace. Upper and lower ends of the mechanical test device are connected in a top of the bearing frame and the bottom of the high-temperature furnace. A sample is connected and mounted at an end of the mechanical test device.

Abstract: A far-end data migration device and method based on a FPGA cloud platform. The device includes a server, a switch, and a plurality of FPGA acceleration cards. The server transmits data to be accelerated to the FPGA acceleration cards by means of the switch. The FPGA acceleration cards are configured to perform a primary and/or secondary acceleration on the data, and are configured to migrate the accelerated data. The method includes: transmitting data to be accelerated to a FPGA acceleration card from a server by means of a switch; performing, by the FPGA acceleration card, a primary and/or secondary acceleration on the data to be accelerated; and migrating, by the FPGA acceleration card, the accelerated data.

Abstract: Disclosed is an Avalon-to-Axi4 bus conversion method, including: in case that an Avalon bus is an Avalon_st bus, receiving Avalon_st bus data, performing a logical process on the received Avalon_st bus data, and then outputting corresponding Axi4_st bus data; and in case that the Avalon bus is an Avalon_mm bus, receiving a signal transmitted by each channel of the Avalon_mm bus, framing and storing the signal in asynchronous First Input First Output (FIFO), and in case that a device corresponding to an Axi4 bus is ready, reading the signal from the asynchronous FIFO, and outputting the signal to a corresponding channel of the Axi4 bus according to a timing relationship of the Axi4 bus.

Abstract: A compound represented by formula (I), an optical isomer thereof and a pharmaceutically acceptable salt thereof, as well as an application of said compound as an FXIa inhibitor.

Abstract: Provided is a material performance testing system under a fixed multi-field coupling effect in a hypergravity environment, including a hoisted sealed cabin, a bearing frame, a high-temperature furnace, a mechanical test device, and a buffer device. The bearing frame and the high-temperature furnace are fixedly mounted inside the hoisted sealed cabin. The bearing frame is covered on the high-temperature furnace. The buffer device is mounted at a bottom of the high-temperature furnace. Upper and lower ends of the mechanical test device are connected in a top of the bearing frame and the bottom of the high-temperature furnace. A sample is connected and mounted at an end of the mechanical test device.

Abstract: A compound represented by formula (I), an optical isomer thereof and a pharmaceutically acceptable salt thereof, as well as an application of said compound as an FXIa inhibitor.

Abstract: Provided is a supergravity directional solidification melting furnace equipment, including a supergravity test chamber and, mounted in the supergravity test chamber, a high-temperature heating subsystem, a crucible, and an air-cooling system. The supergravity test chamber is mounted with a wiring electrode and a cooling air valve device. The high-temperature heating subsystem is fixed in the supergravity test chamber. The crucible and the air cooling system are provided in the high-temperature heating subsystem. The high-temperature heating subsystem includes upper, middle, and lower furnaces, a mullite insulating layer, upper and lower heating cavity outer bodies, upper and lower heating furnace pipes, and a crucible support base. A high-temperature heating cavity is divided into upper and lower parts, is provided therein with a spiral groove, and is fitted with a heating element. The crucible support base is provided therein with a vent pipe channel into which a cooling air is introduced.

Abstract: The present disclosure relates to pyridinamine-substituted heterotricyclo compounds, a preparation method thereof, and a use thereof in medicines. Specifically, a compound of formula (I), or a pharmaceutically acceptable salt, stereoisomer, solvate, or prodrug thereof, a preparation method and a use thereof are disclosed, wherein the groups in the formula (I) are as defined in the Description and claims.

Abstract: The present disclosure relates to pyridinamine-substituted heterotricyclo compounds, a preparation method thereof, and a use thereof in medicines. Specifically, a compound of formula (I), or a pharmaceutically acceptable salt, stereoisomer, solvate, or prodrug thereof, a preparation method and a use thereof are disclosed, wherein the groups in the formula (I) are as defined in the Description and claims.