Patents by Inventor Jiangyuan Zhang

Jiangyuan Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8674490
    Abstract: A semiconductor die package. Embodiments of the semiconductor die package are usable in backlight circuitry. Systems in packages may include a bridge circuit or a part thereof, and a integrated circuit die, such as a driver die, encapsulated by a molding material or other package. The bridge circuit may be stacked on opposing surfaces of a leadframe.
    Type: Grant
    Filed: February 24, 2011
    Date of Patent: March 18, 2014
    Assignee: Fairchild Semiconductor Corporatio
    Inventors: Yong Liu, Jiangyuan Zhang, Qiuxiao Qian
  • Patent number: 8399997
    Abstract: In one embodiment, a method includes attaching a film to cover a first portion of a first semiconductor die. The first semiconductor die is attached, using the tape, to a lead frame using a first bonding method. The first bonding method places the film between the lead frame and the semiconductor die. A second semiconductor die is attached to the lead frame using a second bonding method. The second bonding method bonds the lead frame and the semiconductor die. The first semiconductor device and the second semiconductor device are encapsulated into a semiconductor package.
    Type: Grant
    Filed: June 10, 2011
    Date of Patent: March 19, 2013
    Assignee: Shanghai Kalhong Electronic Company Limited
    Inventors: Jiangyuan Zhang, Elite Lee, Dana Liu
  • Patent number: 8367481
    Abstract: A molded, leadless packaged semiconductor multichip module includes 100 has four mosfets 10, 12, 14, 16 for a full bridge circuit. The mosfets may include two N-channel and two P-channel devices or four mosfets of the same type, but four N-channel are preferred. In module 100 there are two leadframes 30, 40 for assembling the mosfets. In particular, the two N-channel and two P-channel devices are disposed between two leadframes and encapsulated in an electrically insulating molding compound 84. The resulting package has four upper heat sinks 44.1-44.4 that are exposed in the molding compound 84 for transferring heat from the mosfets to the ambient environment. No wire bonds are required. This can significantly reduce the on resistance, RDSON. The top or source-drain lead frame 30 may be soldered to the sources and gates of the bridge mosfets.
    Type: Grant
    Filed: February 15, 2012
    Date of Patent: February 5, 2013
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Yong Liu, Qiuxiao Qian, JiangYuan Zhang, Mike Speed, JungTae Lee, Luke Huiyong Chung
  • Publication number: 20130005083
    Abstract: A molded, leadless packaged semiconductor multichip module includes 100 has four mosfets 10, 12, 14, 16 for a full bridge circuit. The mosfets may include two N-channel and two P-channel devices or four mosfets of the same type, but four N-channel are preferred. In module 100 there are two leadframes 30, 40 for assembling the mosfets. In particular, the two N-channel and two P-channel devices are disposed between two leadframes and encapsulated in an electrically insulating molding compound 84. The resulting package has four upper heat sinks 44.1-44.4 that are exposed in the molding compound 84 for transferring heat from the mosfets to the ambient environment. No wire bonds are required. This can significantly reduce the on resistance, RDSON. The top or source-drain lead frame 30 may be soldered to the sources and gates of the bridge mosfets.
    Type: Application
    Filed: February 15, 2012
    Publication date: January 3, 2013
    Inventors: Yong Liu, Qiuxiao Qian, JiangYuan Zhang, Mike Speed, Jung Tae Lee, Luke Huiyong Chung
  • Publication number: 20120315727
    Abstract: In one embodiment, a method for manufacturing a power semiconductor package is provided. The method includes attaching a plurality of solders balls onto a power semiconductor device. The plurality of solder balls are attached onto a lead frame using a flip bond processing step. The flip bond processing step bonds the semiconductor device to the lead frame and interconnects the lead frame to the semiconductor device in a single processing step. The semiconductor device, plurality of solder balls, and the lead frame are molded to form the power semiconductor package, wherein semiconductor device is exposed on a first side of the semiconductor package.
    Type: Application
    Filed: June 10, 2011
    Publication date: December 13, 2012
    Applicant: SHANGHAI KAIHONG ELECTRONIC COMPANY LIMITED
    Inventors: Jiangyuan Zhang, Elite Lee, Dana Liu
  • Publication number: 20120313232
    Abstract: In one embodiment, a method includes attaching a film to cover a first portion of a first semiconductor die. The first semiconductor die is attached, using the tape, to a lead frame using a first bonding method. The first bonding method places the film between the lead frame and the semiconductor die. A second semiconductor die is attached to the lead frame using a second bonding method. The second bonding method bonds the lead frame and the semiconductor die. The first semiconductor device and the second semiconductor device are encapsulated into a semiconductor package.
    Type: Application
    Filed: June 10, 2011
    Publication date: December 13, 2012
    Applicant: SHANGHAI KAIHONG ELECTRONIC COMPANY LIMITED
    Inventors: Jiangyuan Zhang, Elite Lee, Dana Liu
  • Publication number: 20120149149
    Abstract: A molded, leadless packaged semiconductor multichip module includes 100 has four mosfets 10, 12, 14, 16 for a full bridge circuit. The mosfets may include two N-channel and two P-channel devices or four mosfets of the same type, but four N-channel are preferred. In module 100 there are two leadframes 30, 40 for assembling the mosfets. In particular, the two N-channel and two P-channel devices are disposed between two leadframes and encapsulated in an electrically insulating molding compound 84. The resulting package has four upper heat sinks 44.1-44.4 that are exposed in the molding compound 84 for transferring heat from the mosfets to the ambient environment. No wire bonds are required. This can significantly reduce the on resistance, RDSON. The top or source-drain lead frame 30 may be soldered to the sources and gates of the bridge mosfets.
    Type: Application
    Filed: February 15, 2012
    Publication date: June 14, 2012
    Inventors: Yong Liu, Qiuxiao Qian, JiangYuan Zhang, Mike Speed, Jung Tae Lee, Luke Huiyong Chung
  • Patent number: 8138585
    Abstract: A molded, leadless packaged semiconductor multichip module includes 100 has four mosfets 10, 12, 14, 16 for a full bridge circuit. The mosfets may include two N-channel and two P-channel devices or four mosfets of the same type, but four N-channel are preferred. In module 100 there are two leadframes 30, 40 for assembling the mosfets. In particular, the two N-channel and two P-channel devices are disposed between two leadframes and encapsulated in an electrically insulating molding compound 84. The resulting package has four upper heat sinks 44.1-44.4 that are exposed in the molding compound 84 for transferring heat from the mosfets to the ambient environment. No wire bonds are required. This can significantly reduce the on resistance, RDSON. The top or source-drain lead frame 30 may be soldered to the sources and gates of the bridge mosfets.
    Type: Grant
    Filed: May 28, 2008
    Date of Patent: March 20, 2012
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Yong Liu, Qiuxiao Qian, JiangYuan Zhang, Mike Speed, JungTae Lee, Huiyong Luke Chung
  • Publication number: 20110140255
    Abstract: A semiconductor die package. Embodiments of the semiconductor die package are usable in backlight circuitry. Systems in packages may include a bridge circuit or a part thereof, and a integrated circuit die, such as a driver die, encapsulated by a molding material or other package. The bridge circuit may be stacked on opposing surfaces of a leadframe.
    Type: Application
    Filed: February 24, 2011
    Publication date: June 16, 2011
    Inventors: Yong Liu, Jiangyuan Zhang, Qiuxiao Qian
  • Patent number: 7915721
    Abstract: A semiconductor die package. Embodiments of the semiconductor die package are usable in backlight circuitry. Systems in packages may include a bridge circuit or a part thereof, and a integrated circuit die, such as a driver die, encapsulated by a molding material or other package. The bridge circuit may be stacked on opposing surfaces of a leadframe.
    Type: Grant
    Filed: March 12, 2008
    Date of Patent: March 29, 2011
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Yong Liu, Jiangyuan Zhang, Qiuxiao Qian
  • Publication number: 20090294936
    Abstract: A molded, leadless packaged semiconductor multichip module includes 100 has four mosfets 10, 12, 14, 16 for a full bridge circuit. The mosfets may include two N-channel and two P-channel devices or four mosfets of the same type, but four N-channel are preferred. In module 100 there are two leadframes 30, 40 for assembling the mosfets. In particular, the two N-channel and two P-channel devices are disposed between two leadframes and encapsulated in an electrically insulating molding compound 84. The resulting package has four upper heat sinks 44.1-44.4 that are exposed in the molding compound 84 for transferring heat from the mosfets to the ambient environment. No wire bonds are required. This can significantly reduce the on resistance, RDSON. The top or source-drain lead frame 30 may be soldered to the sources and gates of the bridge mosfets.
    Type: Application
    Filed: May 28, 2008
    Publication date: December 3, 2009
    Inventors: Yong Liu, Qiuxiao Qian, JiangYuan Zhang, Mike Speed, JungTae Lee, Huiyong Luke Chung
  • Publication number: 20090230518
    Abstract: A semiconductor die package. Embodiments of the semiconductor die package are usable in backlight circuitry. Systems in packages may include a bridge circuit or a part thereof, and a integrated circuit die, such as a driver die, encapsulated by a molding material or other package. The bridge circuit may be stacked on opposing surfaces of a leadframe.
    Type: Application
    Filed: March 12, 2008
    Publication date: September 17, 2009
    Inventors: Yong Liu, Jiangyuan Zhang, Qiuxiao Qian