Abstract: A semiconductor device includes an array of VCSEL devices with an annealed oxygen implant region (annealed at a temperature greater than 800° C.) that surrounds and extends laterally between the VCSEL devices. A common anode and a common cathode can be electrically coupled to the VCSEL devices, with the common anode overlying the annealed oxygen implant region. The annealed oxygen implant region can funnel current into active optical regions of the VCSEL devices and provide current isolation between the VCSEL devices while avoiding an isolation etch between VCSEL devices. In another embodiment, a semiconductor device includes an annealed oxygen implant region surrounding a VCSEL device. The VCSEL device(s) can be formed from a multi-junction layer structure where built-in hole charge Qp for an intermediate p-type layer relative to built-in electron charge Qn for a bottom n-type layer is configured for diode-like current-voltage characteristics of the VCSEL device(s).

Abstract: A semiconductor device includes an array of VCSEL devices with an annealed oxygen implant region (annealed at a temperature greater than 800° C.) that surrounds and extends laterally between the VCSEL devices. A common anode and a common cathode can be electrically coupled to the VCSEL devices, with the common anode overlying the annealed oxygen implant region. The annealed oxygen implant region can funnel current into active optical regions of the VCSEL devices and provide current isolation between the VCSEL devices while avoiding an isolation etch between VCSEL devices. In another embodiment, a semiconductor device includes an annealed oxygen implant region surrounding a VCSEL device. The VCSEL device(s) can be formed from a multi-junction layer structure where built-in hole charge Qp for an intermediate p-type layer relative to built-in electron charge Qn for a bottom n-type layer is configured for diode-like current-voltage characteristics of the VCSEL device(s).

Abstract: An optoelectronic circuit includes a resonant cavity formed on a substrate and into which is injected an input digital optical signal that encodes bits of information (each bit representing an OFF logic level or an ON logic level). A heterojunction thyristor device, formed in the resonant cavity, produces an output digital electrical signal corresponding to the input digital optical signal. A sampling clock defines sampling periods that overlap the bits (e.g., ON/OFF pulse durations) in the input digital optical signal. The sampling clock can be in the form of electrical pulses supplied to the n-channel injector terminal(s) and/or p-channel injector terminals of the heterojunction thyristor device. Alternatively, the sampling clock can be in the form of optical pulses that are part of the Optical IN signal that is resonantly absorbed by the device. The heterojunction thyristor device operates in an OFF state and an ON state.

Abstract: Interference caused by the propagation of a transmit signal transmitted from a transmit antenna to a receive antenna is effectively cancelled by an improved signal cancellation system. The system includes an interference cancellation signal generator that generates a time-delayed and amplitude-reduced representation of said transmit signal. A summing stage is operably coupled to the interference cancellation signal generator and the receive antenna. The summing stage subtracts the time-delayed and amplitude-reduced representation of the transmit signal from a receive signal to substantially cancel the interference. The interference cancellation signal generator preferably includes a novel programmable optical delay line that introduces a variable amount of optical delay to an optical signal derived from said transmit signal in addition to a thyristor-based sigma delta modulator that converts samples of the transmit signal to into a digital signal in the optical domain.

Abstract: An optoelectronic circuit includes a resonant cavity formed on a substrate and into which is injected an input digital optical signal that encodes bits of information (each bit representing an OFF logic level or an ON logic level). A heterojunction thyristor device, formed in the resonant cavity, produces an output digital electrical signal corresponding to the input digital optical signal. A sampling clock defines sampling periods that overlap the bits (e.g., ON/OFF pulse durations) in the input digital optical signal. The sampling clock can be in the form of electrical pulses supplied to the n-channel injector terminal(s) and/or p-channel injector terminals of the heterojunction thyristor device. Alternatively, the sampling clock can be in the form of optical pulses that are part of the Optical IN signal that is resonantly absorbed by the device. The heterojunction thyristor device operates in an OFF state and an ON state.

Abstract: An optoelectronic circuit includes a resonant cavity formed on a substrate and into which is injected an input digital optical signal that encodes bits of information (each bit representing an OFF logic level or an ON logic level). A heterojunction thyristor device, formed in the resonant cavity, produces an output digital electrical signal corresponding to the input digital optical signal. A sampling clock defines sampling periods that overlap the bits (e.g., ON/OFF pulse durations) in the input digital optical signal. The sampling clock can be in the form of electrical pulses supplied to the n-channel injector terminal(s) and/or p-channel injector terminals of the heterojunction thyristor device. Alternatively, the sampling clock can be in the form of optical pulses that are part of the Optical IN signal that is resonantly absorbed by the device. The heterojunction thyristor device operates in an OFF state and an ON state.

Abstract: Interference caused by the propagation of a transmit signal transmitted from a transmit antenna to a receive antenna is effectively cancelled by an improved signal cancellation system. The system includes an interference cancellation signal generator that generates a time-delayed and amplitude-reduced representation of said transmit signal. A summing stage is operably coupled to the interference cancellation signal generator and the receive antenna. The summing stage subtracts the time-delayed and amplitude-reduced representation of the transmit signal from a receive signal to substantially cancel the interference. The interference cancellation signal generator preferably includes a novel programmable optical delay line that introduces a variable amount of optical delay to an optical signal derived from said transmit signal in addition to a thyristor-based sigma delta modulator that converts samples of the transmit signal to into a digital signal in the optical domain.

Abstract: Interference caused by the propagation of a transmit signal transmitted from a transmit antenna to a receive antenna is effectively cancelled by an improved signal cancellation system. The system includes an interference cancellation signal generator that generates a time-delayed and amplitude-reduced representation of said transmit signal. A summing stage is operably coupled to the interference cancellation signal generator and the receive antenna. The summing stage subtracts the time-delayed and amplitude-reduced representation of the transmit signal from a receive signal to substantially cancel the interference. The interference cancellation signal generator preferably includes a novel programmable optical delay line that introduces a variable amount of optical delay to an optical signal derived from said transmit signal in addition to a thyristor-based sigma delta modulator that converts samples of the transmit signal to into a digital signal in the optical domain.

Abstract: A photonic digital-to-analog converter employing a plurality of heterojunction thyristor devices that are configured to convert a digital word encoded by a parallel digital optical signal (e.g., a plurality of synchronous optical bits) to an output analog electrical signal whose magnitude corresponds to the digital word. Each heterojunction thyristor device is configured to convert an optical bit in the digital word to a corresponding digital electrical signal. The voltage levels (e.g., magnitudes) of the ON state of the digital electrical signals produced by the heterojunction thyristor devices may be supplied by voltage divider networks coupled between the cathode terminal of the devices and ground potential or voltage reference sources coupled to the input terminals of the heterojunction thyristor devices. In this manner, electrical signals whose magnitude corresponds to contribution of each optical bit in the digital word are produced.

Abstract: An optoelectronic integrated circuit includes a resonant cavity formed on a substrate. A heterojunction thyristor device is formed in the resonant cavity and operates to detect an input optical pulse (or input electrical pulse) and produce an output optical pulse via laser emission in response to the detected input pulse. The heterojunction thyristor device includes a channel region that is coupled to a current source that draws current from the channel region. Time delay between the input pulse and output optical pulse may be varied by configuring the current source to draw constant current from the channel region and modulating the intensity of the input pulse, or by varying the amount of current drawn from the channel region by the current source. The heterojunction thyristor device may be formed from a multilayer structure of group III-V materials, or from a multilayer structure of strained silicon materials.

Abstract: A serial photonic digital-to-analog converter employs a heterojunction thyristor device configured for optically-controlled sampling/switching to convert a digital word encoded by a serial digital optical data signal (e.g., serial optical bit stream) into a corresponding analog electrical signal. A voltage reference is operably coupled to the electrical input terminal of the heterojunction thyristor device. The voltage reference cooperates with the heterojunction thyristor device to sequentially generate at its electrical output terminal a voltage signal representing contribution of each bit of the digital word encoded in the serial digital optical data signal. A summing network is operably coupled to the electrical output terminal of the device. The summing network sequentially sums contribution of the voltage signal over the sequence of bits to produce an analog electrical signal corresponding to the digital word for output therefrom.

Abstract: An optoelectronic circuit employing a heterojunction thyristor device that is configured as an optically-controlled (or electrically-controlled) sampling/switching device. First and second channel regions are disposed between the anode terminal and the cathode terminal of the device, and an electrical input terminal and an electrical output terminal are coupled to opposite ends of the first channel region. At least one control signal is supplied to the device. When the control signal corresponds to a predetermined ON condition, sufficient charge is stored in the second channel region to cause the heterojunction thyristor device to operate in an ON state whereby current flows between the anode terminal and the cathode terminal and the electrical input terminal is electrically coupled to the electrical output terminal.

Abstract: An integrated circuit includes a heterojunction thyristor device having an anode terminal, a cathode terminal, a first injector terminal operably coupled to a first quantum well channel disposed between the anode terminal and the cathode terminal, and a second injector terminal operably coupled to a second quantum well channel disposed between the anode terminal and the cathode terminal. Bias elements operate the heterojunction thyristor device in a mode that provides substantially linear voltage gain for electrical signals supplied to at least one of the first and second injector terminals for output to at least one output node.

Abstract: An integrated circuit includes a heterojunction thyristor device having an anode terminal, a cathode terminal, a first injector terminal operably coupled to a first quantum well channel disposed between the anode terminal and the cathode terminal, and a second injector terminal operably coupled to a second quantum well channel disposed between the anode terminal and the cathode terminal. Bias elements operate the heterojunction thyristor device in a mode that provides substantially linear voltage gain for electrical signals supplied to at least one of the first and second injector terminals for output to at least one output node.

Abstract: Interference caused by the propagation of a transmit signal transmitted from a transmit antenna to a receive antenna is effectively cancelled by an improved signal cancellation system. The system includes an interference cancellation signal generator that generates a time-delayed and amplitude-reduced representation of said transmit signal. A summing stage is operably coupled to the interference cancellation signal generator and the receive antenna. The summing stage subtracts the time-delayed and amplitude-reduced representation of the transmit signal from a receive signal to substantially cancel the interference. The interference cancellation signal generator preferably includes a novel programmable optical delay line that introduces a variable amount of optical delay to an optical signal derived from said transmit signal in addition to a thyristor-based sigma delta modulator that converts samples of the transmit signal to into a digital signal in the optical domain.

Abstract: An optoelectronic circuit includes a resonant cavity formed on a substrate and into which is injected an input digital optical signal that encodes bits of information (each bit representing an OFF logic level or an ON logic level). A heterojunction thyristor device, formed in the resonant cavity, produces an output digital electrical signal corresponding to the input digital optical signal. A sampling clock defines sampling periods that overlap the bits (e.g., ON/OFF pulse durations) in the input digital optical signal. The sampling clock can be in the form of electrical pulses supplied to the n-channel injector terminal(s) and/or p-channel injector terminals of the heterojunction thyristor device. Alternatively, the sampling clock can be in the form of optical pulses that are part of the Optical IN signal that is resonantly absorbed by the device. The heterojunction thyristor device operates in an OFF state and an ON state.

Abstract: A serial photonic digital-to-analog converter employs a heterojunction thyristor device configured for optically-controlled sampling/switching to convert a digital word encoded by a serial digital optical data signal (e.g., serial optical bit stream) into a corresponding analog electrical signal. A voltage reference is operably coupled to the electrical input terminal of the heterojunction thyristor device. The voltage reference cooperates with the heterojunction thyristor device to sequentially generate at its electrical output terminal a voltage signal representing contribution of each bit of the digital word encoded in the serial digital optical data signal. A summing network is operably coupled to the electrical output terminal of the device. The summing network sequentially sums contribution of the voltage signal over the sequence of bits to produce an analog electrical signal corresponding to the digital word for output therefrom.

Abstract: An optoelectronic integrated circuit includes a resonant cavity formed on a substrate. A heterojunction thyristor device is formed in the resonant cavity and operates to detect an input optical pulse (or input electrical pulse) and produce an output optical pulse via laser emission in response to the detected input pulse. The heterojunction thyristor device includes a channel region that is coupled to a current source that draws current from the channel region. Time delay between the input pulse and output optical pulse may be varied by configuring the current source to draw constant current from the channel region and modulating the intensity of the input pulse, or by varying the amount of current drawn from the channel region by the current source. The heterojunction thyristor device may be formed from a multilayer structure of group III-V materials, or from a multilayer structure of strained silicon materials.

Abstract: A photonic digital-to-analog converter employing a plurality of heterojunction thyristor devices that are configured to convert a digital word encoded by a parallel digital optical signal (e.g., a plurality of synchronous optical bits) to an output analog electrical signal whose magnitude corresponds to the digital word. Each heterojunction thyristor device is configured to convert an optical bit in the digital word to a corresponding digital electrical signal. The voltage levels (e.g., magnitudes) of the ON state of the digital electrical signals produced by the heterojunction thyristor devices may be supplied by voltage divider networks coupled between the cathode terminal of the devices and ground potential or voltage reference sources coupled to the input terminals of the heterojunction thyristor devices. In this manner, electrical signals whose magnitude corresponds to contribution of each optical bit in the digital word are produced.

Abstract: An optoelectronic circuit employing a heterojunction thyristor device that is configured as an optically-controlled (or electrically-controlled) sampling/switching device. First and second channel regions are disposed between the anode terminal and the cathode terminal of the device, and an electrical input terminal and an electrical output terminal are coupled to opposite ends of the first channel region. At least one control signal is supplied to the device. When the control signal corresponds to a predetermined ON condition, sufficient charge is stored in the second channel region to cause the heterojunction thyristor device to operate in an ON state whereby current flows between the anode terminal and the cathode terminal and the electrical input terminal is electrically coupled to the electrical output terminal.