Abstract: The present invention provides a system and method for analysis of integrated circuit testing anomalies based on deep learning. Through repeated training by deep learning with historical test data accumulated during testing, automatic optimization of parameter settings depending on learning and training conditions is made possible. Moreover, based on real-time test data, testing anomalies can be predicted and early warnings against them can be provided to allow advanced intervention for preventing their occurrence. Additionally, for testing anomalies that have occurred, solutions can be automatically identified and provided, which shorten the times taken by different technicians to address the anomalies, resulting in more effective utilization of the equipment and lower testing cost.

Abstract: The invention relates to a universal semiconductor automatic high-speed serial signal testing method, comprising: a chip to be tested sending, to an impedance matching unit, a high-speed serial signal; then by means of a phase shift unit, sequentially transforming, according to a set fixed resolution, the phase of the high-speed serial signal, the magnitude of each offset phase being determined by a phase shift control signal outputted by a control unit and the resolution of the phase shift unit; after passing through the phase shift unit, the high-speed serial signal keeps channel impedance matching by means of the impedance matching unit; the signal entering an acquisition unit, and being acquired under the action of an acquisition control signal sent by the control unit; the control unit performing signal exchange with semiconductor automatic testing equipment (ATE); and the acquisition unit transmitting the acquired signal back to the universal semiconductor ATE for algorithm operation, and then the actua

Abstract: The present invention discloses an information management method and system for IC tests, and a storage medium. The method comprises steps of: providing test data generated by performing an IC test by an IC test platform, the IC test platform being an IC test platform having more than one stage, each stage of the IC test platform comprising a plurality of test devices: providing resource data related to the IC test, other than the test data; and analyzing the IC test according to the test data of the IC test and the resource data, to obtain result data related to the IC test. In this way, the present invention can provide technical support for utilizing the value of test data generated in IC tests.

Abstract: The invention relates to a universal semiconductor automatic high-speed serial signal testing method, comprising: a chip to be tested sending, to an impedance matching unit, a high-speed serial signal; then by means of a phase shift unit, sequentially transforming, according to a set fixed resolution, the phase of the high-speed serial signal, the magnitude of each offset phase being determined by a phase shift control signal outputted by a control unit and the resolution of the phase shift unit; after passing through the phase shift unit, the high-speed serial signal keeps channel impedance matching by means of the impedance matching unit; the signal entering an acquisition unit, and being acquired under the action of an acquisition control signal sent by the control unit; the control unit performing signal exchange with semiconductor automatic testing equipment (ATE); and the acquisition unit transmitting the acquired signal back to the universal semiconductor ATE for algorithm operation, and then the actua

Abstract: The present invention relates to an optimization method for an integrated circuit wafer test, which is applied in an integrated circuit wafer test process. By means of pre-specifying and storing coordinates of a die to be tested on a wafer in a test system, then testing the pre-specified die according to a design map by means of a test process, and adjusting in real time a range of pre-specified coordinates according to a test result of a current die, a desired test coordinate map is finally obtained so as to cover the maximum number of fail dies in an optimized solution, thereby reducing test time, improving testing efficiency, reducing the frequency of testing hardware usage and increasing service life. By means of calculating a suitable coverage number in the present invention, a smaller number of fail chips that reach a package will also be obtained without increasing the cost of the package. At the same time, the number of probe card tests is reduced, and the hardware service life is increased.

Abstract: The present invention discloses an information management method and system for IC tests, and a storage medium. The method comprises steps of: providing test data generated by performing an IC test by an IC test platform, the IC test platform being an IC test platform having more than one stage, each stage of the IC test platform comprising a plurality of test devices: providing resource data related to the IC test, other than the test data; and analyzing the IC test according to the test data of the IC test and the resource data, to obtain result data related to the IC test. In this way, the present invention can provide technical support for utilizing the value of test data generated in IC tests.

Abstract: An embedded LED downlight disclosed herein includes a main housing and a junction box fixedly connected to each other, wherein the main housing is of cylindrical structure having an open end, a closed end and an accommodating space formed therein; a light transmission component is fixed to an opening at the open end; an LED light-emitting assembly and an IC constant-current power supply are disposed in the accommodating space; the closed end of the main housing is fixedly connected to the junction box; spring clips are hinged at symmetrical positions on an outer circumferential surface of the main housing close to the opening, respectively; and the main housing and the junction box are both made of flame-resistant plastic material at a fireproofing grade of 5VA.

Abstract: An embedded LED downlight disclosed herein includes a main housing and a junction box fixedly connected to each other, wherein the main housing is of cylindrical structure having an open end, a closed end and an accommodating space formed therein; a light transmission component is fixed to an opening at the open end; an LED light-emitting assembly and an IC constant-current power supply are disposed in the accommodating space; the closed end of the main housing is fixedly connected to the junction box; spring clips are hinged at symmetrical positions on an outer circumferential surface of the main housing close to the opening, respectively; and the main housing and the junction box are both made of flame-resistant plastic material at a fireproofing grade of 5VA.

Abstract: An IEEE 1149.1 standard based testing method used in packaging is disclosed. The method includes adding a TRD pin to each of n devices up to the IEEE 1149.1 standard. The TRD pins of the n devices are connected together to a common output terminal which is connected to a testing system. The first to m-th ones of the devices are tested by connecting the TDO and TRD pins of the m-th device and disconnecting the TDO and TRD pins of any one of the n devices other than the m-th, wherein m is a natural number that is smaller than or equal to n.

Abstract: A test apparatus with physical separation feature is disclosed. The test apparatus includes probes (210), a peripheral circuit (220), a circuit of special function (230), wherein the peripheral circuit and the circuit of special function are separately arranged on different circuit boards (240, 250). The peripheral circuit and the circuit of special function are both electrically connected to the probes. In the test apparatus with physical separation feature, the peripheral circuit and the circuit of special function are separated in physical spaces, so that interference between the components is prevented and the testing cost is reduced.

Abstract: A compression method for compressing an original test file is disclosed. The compression method includes the following steps: defining type modules; scanning the original test file line by line in bytes and matching data of the original test file with the type modules to determine types of the data; compressing continuous data of the same type in lines and representing each compressed portion with a thumbnail. The compression method enables a browser to read test files with a fast speed by compressing test files according to the types of data.

Abstract: A test apparatus with physical separation feature is disclosed. The test apparatus includes probes (210), a peripheral circuit (220), a circuit of special function (230), wherein the peripheral circuit and the circuit of special function are separately arranged on different circuit boards (240, 250). The peripheral circuit and the circuit of special function are both electrically connected to the probes. In the test apparatus with physical separation feature, the peripheral circuit and the circuit of special function are separated in physical spaces, so that interference between the components is prevented and the testing cost is reduced.