Abstract: The present application discloses a full adder circuit and a multi-bit full adder. In the full adder circuit, an in-memory computing field-effect transistor stores data and performs logic operation on the data in the transistor and the loaded data according to different input signals; and a low-area full adder circuit is realized with very few transistors through the characteristics and the reading and writing modes of the in-memory computing field-effect transistor. The full adder circuit has a simple structure, which is greatly reduces the area and complexity of the full adder circuit, and saves 19 transistors compared with the traditional CMOS full adder circuits.

Abstract: A flip-flop element is configured to gate the clock inversions within a master-slave flip-flop element. The flip-flop element reduces the number of circuit elements within the flip-flop element by collapsing elements with common functionality into a single circuit element. Further, by making the actions of judiciously selected circuit elements conditional upon the state of the input data, the flip-flop element circuit reduces the number of internal transitions. In this manner, by reducing the number of circuit elements as well as the number of transitions, the flip-flop element achieves substantial reduction in overall system power consumption, resulting in a more efficient system.

Abstract: A flip-flop element is configured to include FinFET technology transistors with a mix of threshold voltage levels. The data input path includes FinFET transistors configured with high voltage thresholds (HVT). The clock input path includes transistors configured with standard voltage thresholds (SVT). By including FinFET transistors with SVT thresholds in the clock signal path, the Miller capacitance of the clock signal path is reduced relative to HVT FinFET transistors, leading to lower rise time and correspondingly lower hold time. By including HVT threshold devices in the data input path, the flip-flop element attains high speed and low power operation. By including SVT threshold devices in the clock signal path, the flip-flop element achieves faster switching times in the clock signal path.

Abstract: Mitigating external influences on long signal lines. In accordance with an embodiment of the present invention, a column of a memory array includes first and second transistors configured to pull up the bit line of the column. The column includes a third transistor configured to selectively pull up the bit line of the column responsive to a level of the inverted bit line of the column and a fourth transistor configured to selectively pull up the inverted bit line of the column responsive to a level of the bit line of the column. The column further includes fifth and sixth transistors configured to selectively pull up the bit line and inverted bit line of the column responsive to the clamp signal and a seventh transistor configured to selectively couple the bit line of the column and the inverted bit line of the column responsive to the clamp signal.

Abstract: A flip-flop element is configured to include FinFET technology transistors with a mix of threshold voltage levels. The data input path includes FinFET transistors configured with high voltage thresholds (HVT). The clock input path includes transistors configured with standard voltage thresholds (SVT). By including FinFET transistors with SVT thresholds in the clock signal path, the Miller capacitance of the clock signal path is reduced relative to HVT FinFET transistors, leading to lower rise time and correspondingly lower hold time. By including HVT threshold devices in the data input path, the flip-flop element attains high speed and low power operation. By including SVT threshold devices in the clock signal path, the flip-flop element achieves faster switching times in the clock signal path.

Abstract: A flip-flop element is configured to gate the clock inversions within a master-slave flip-flop element. The flip-flop element reduces the number of circuit elements within the flip-flop element by collapsing elements with common functionality into a single circuit element. Further, by making the actions of judiciously selected circuit elements conditional upon the state of the input data, the flip-flop element circuit reduces the number of internal transitions. In this manner, by reducing the number of circuit elements as well as the number of transitions, the flip-flop element achieves substantial reduction in overall system power consumption, resulting in a more efficient system.

Abstract: The steam valve driving device of this embodiment adjusts a flow rate of steam flowing inside a valve box by varying a distance between a valve seat and a valve element connected to a valve stem in the valve box. The steam valve driving device has an oil cylinder and a spring box. Here, an inlet and an outlet are formed in the spring box. Then, the air from the outside of the spring box is supplied into the spring box from the inlet of the spring box so as to make a pressure in the spring box higher than that of the outside, and is discharged from the outlet of the spring box.

Abstract: A scan flip-flop circuit comprises a scan input sub-circuit and a selection sub-circuit. The scan input sub-circuit is configured to receive a scan input signal and a scan enable signal and, when the scan enable signal is activated, generate complementary scan input signals representing the scan input signal that are delayed relative to a transition of a clock input signal between two different logic levels. The selection sub-circuit is coupled to the scan input sub-circuit and configured to receive the complementary scan input signals and, based on the scan enable signal, output an inverted version of either the scan input signal or a data signal as a first selected input signal.

Abstract: Provided herein is a voltage level shifter, an apparatus including a voltage level shifter and a method of converting voltages between input and output power domains. In one embodiment, the voltage level shifter includes: (1) an input circuit configured to receive a data signal from an input power domain and a power down signal from a output power domain and (2) a transition circuit coupled to the input circuit and configured to receive the data signal and an inverted signal of the power down signal, wherein the input circuit and the transition circuit are both configured to connect to a supply voltage of the output power domain as a power source.

Abstract: Small area low power data retention flop. In accordance with a first embodiment of the present invention, a circuit includes a master latch coupled to a data retention latch. The data retention latch is configured to operate as a slave latch to the master latch to implement a master-slave flip flop during normal operation. The data retention latch is configured to retain an output value of the master-slave flip flop during a low power data retention mode when the master latch is powered down. A single control input is configured to select between the normal operation and the low power data retention mode. The circuit may be independent of a third latch.

Abstract: A dual flip-flop circuit combines two or more flip-flip sub-circuits into a single circuit. The flip-flop circuit comprises a first flip-flop sub-circuit and a second flip-flop sub-circuit. The first flip-flop sub-circuit comprises a first storage sub-circuit configured to store a first selected input signal and transfer the first selected input signal to a first output signal when a buffered clock signal transitions between two different logic levels and a dock driver configured to receive a clock input signal, generate an inverted clock signal, and generate the buffered clock signal. The second flip-flop sub-circuit is coupled to the clock driver and configured to receive the inverted clock signal and the buffered clock signal. The second flip-flop sub-circuit comprises a second storage sub-circuit configured to store a second selected input signal and transfer the second selected input signal to a second output signal when the buffered clock signal transitions.

Abstract: Small area low power data retention flop. In accordance with a first embodiment of the present invention, a circuit includes a master latch coupled to a data retention latch. The data retention latch is configured to operate as a slave latch to the master latch to implement a master-slave flip flop during normal operation. The data retention latch is configured to retain an output value of the master-slave flip flop during a low power data retention mode when the master latch is powered down. A single control input is configured to select between the normal operation and the low power data retention mode. The circuit may be independent of a third latch.

Abstract: Mitigating external influences on long signal lines. In accordance with an embodiment of the present invention, a column of a memory array includes first and second transistors configured to pull up the bit line of the column. The column includes a third transistor configured to selectively pull up the bit line of the column responsive to a level of the inverted bit line of the column and a fourth transistor configured to selectively pull up the inverted bit line of the column responsive to a level of the bit line of the column. The column further includes fifth and sixth transistors configured to selectively pull up the bit line and inverted bit line of the column responsive to the clamp signal and a seventh transistor configured to selectively couple the bit line of the column and the inverted bit line of the column responsive to the clamp signal.

Abstract: A scan flip-flop circuit comprises a scan input sub-circuit and a selection sub-circuit. The scan input sub-circuit is configured to receive a scan input signal and a scan enable signal and, when the scan enable signal is activated, generate complementary scan input signals representing the scan input signal that are delayed relative to a transition of a clock input signal between two different logic levels. The selection sub-circuit is coupled to the scan input sub-circuit and configured to receive the complementary scan input signals and, based on the scan enable signal, output an inverted version of either the scan input signal or a data signal as a first selected input signal.

Abstract: A dual flip-flop circuit combines two or more flip-flip sub-circuits into a single circuit. The flip-flop circuit comprises a first flip-flop sub-circuit and a second flip-flop sub-circuit. The first flip-flop sub-circuit comprises a first storage sub-circuit configured to store a first selected input signal and transfer the first selected input signal to a first output signal when a buffered clock signal transitions between two different logic levels and a dock driver configured to receive a clock input signal, generate an inverted clock signal, and generate the buffered clock signal. The second flip-flop sub-circuit is coupled to the clock driver and configured to receive the inverted clock signal and the buffered clock signal. The second flip-flop sub-circuit comprises a second storage sub-circuit configured to store a second selected input signal and transfer the second selected input signal to a second output signal when the buffered clock signal transitions.

Abstract: Provided herein is a voltage level shifter, an apparatus including a voltage level shifter and a method of converting voltages between input and output power domains. In one embodiment, the voltage level shifter includes: (1) an input circuit configured to receive a data signal from an input power domain and a power down signal from a output power domain and (2) a transition circuit coupled to the input circuit and configured to receive the data signal and an inverted signal of the power down signal, wherein the input circuit and the transition circuit are both configured to connect to a supply voltage of the output power domain as a power source.