Abstract: Methods of critical dimension (CD) uniformity control for magnetic head devices are disclosed. In some embodiments, a method can include providing a film stack, the film stack including a substrate, a magnetoresistive (MR) sensor layer, and a hard mask layer, patterning the hard mask layer using a first mask that defines critical shape patterns other than the CD, forming a mandrel pattern using a second mask that defines the CD, and forming a sidewall spacer pattern on sidewalls of the mandrel pattern, and removing the mandrel pattern.

Abstract: Methods of critical dimension (CD) uniformity control for magnetic head devices are disclosed. In some embodiments, a method can include providing a film stack, the film stack including a substrate, a magnetoresistive (MR) sensor layer, and a hard mask layer, patterning the hard mask layer using a first mask that defines critical shape patterns other than the CD, forming a mandrel pattern using a second mask that defines the CD, and forming a sidewall spacer pattern on sidewalls of the mandrel pattern, and removing the mandrel pattern.

Abstract: Methods of critical dimension (CD) uniformity control for magnetic head devices are disclosed. In some embodiments, a method can include providing a film stack, the film stack including a substrate, a magnetoresistive (MR) sensor layer, and a hard mask layer, patterning the hard mask layer using a first mask that defines critical shape patterns other than the CD, forming a mandrel pattern using a second mask that defines the CD, and forming a sidewall spacer pattern on sidewalls of the mandrel pattern, and removing the mandrel pattern.

Abstract: Disclosed are a digital audio power amplifier and a power amplifier loop.

Abstract: A detection circuit and an electronic device using the detection circuit are provided. The detection circuit includes a fourth branch, a fifth branch and a third energy storage unit. The fourth branch includes multiple fourth switches, and the fifth branch includes multiple fifth switches. A preset electrical signal threshold is sampled and applied to the third energy storage unit by controlling the multiple fourth switches in the fourth branch, and a voltage difference between two detection terminals of a first energy storage unit is sampled and applied to the third energy storage unit by controlling the multiple fifth switches in the fifth branch, to compare the voltage difference between the two detection terminals with the preset electrical signal threshold.

Abstract: A detection circuit and an electronic device using the detection circuit are provided. The detection circuit includes a fourth branch, a fifth branch and a third energy storage unit. The fourth branch includes multiple fourth switches, and the fifth branch includes multiple fifth switches. A preset electrical signal threshold is sampled and applied to the third energy storage unit by controlling the multiple fourth switches in the fourth branch, and a voltage difference between two detection terminals of a first energy storage unit is sampled and applied to the third energy storage unit by controlling the multiple fifth switches in the fifth branch, to compare the voltage difference between the two detection terminals with the preset electrical signal threshold.

Abstract: This document discusses, among other things, apparatus and methods for restarting an electronic device configured to receive power from a main power supply and an auxiliary power supply. The electronic device includes a reset circuit a reset circuit configured to provide a first signal indicative of an electronic device failure, and an isolation circuit configured to isolate the main power supply from the auxiliary power supply in response to the first signal so that power is supplied to the reset circuit by the auxiliary power supply. The reset circuit can be configured to generate a reset signal for restarting the electronic device with the power supplied by the auxiliary power supply.

Abstract: This document discusses, among other things, an impedance detection circuit, method, and integrated circuit, comprising a ramp-up current generation circuit and an impedance determining circuit, wherein the ramp-up current generation circuit is configured to input a ramp-up current including n breaks to a port of a device where the ramp-up current generation circuit is disposed, to which port an external device is connected, and wherein the impedance determining circuit is configured to detect an impedance of the external device in each break time period of the ramp-up current input by the ramp-up current generation circuit until the impedance of the external device is acquired by detection in the last break time period of the n breaks.

Abstract: This document discusses, among other things, a voltage comparator, an integrated circuit, or a voltage comparison method having increased precision. The hysteresis comparator or the integrated circuit can include first and second input transistors, each having a gate configured to receive a respective first or second input voltage. A bias power source can generate a bias current to a first node by applying a voltage through a first resistor. The first node can be connected to a source of the first input transistor through a second resistor and to a source of the second input transistor through a third resistor. The first, second, and third resistors can include the same type of resistor, with the second and third resistors having different resistance values.

Abstract: This document discusses, among other things, apparatus and methods for restarting an electronic device configured to receive power from a main power supply and an auxiliary power supply. The electronic device includes a reset circuit a reset circuit configured to provide a first signal indicative of an electronic device failure, and an isolation circuit configured to isolate the main power supply from the auxiliary power supply in response to the first signal so that power is supplied to the reset circuit by the auxiliary power supply. The reset circuit can be configured to generate a reset signal for restarting the electronic device with the power supplied by the auxiliary power supply.

Abstract: This document discusses, among other things, a voltage comparator, an integrated circuit, or a voltage comparison method having increased precision. The hysteresis comparator or the integrated circuit can include first and second input transistors, each having a gate configured to receive a respective first or second input voltage. A bias power source can generate a bias current to a first node by applying a voltage through a first resistor. The first node can be connected to a source of the first input transistor through a second resistor and to a source of the second input transistor through a third resistor. The first, second, and third resistors can include the same type of resistor, with the second and third resistors having different resistance values.

Abstract: A thermally assisted magnetic recording head is disclosed having a spot size converter with at least one secondary waveguide adjoining a top or bottom surface of a primary waveguide. Each waveguide has tapered sides but the secondary waveguide is tapered at a greater angle over a shorter taper distance in order to couple propagated light into the primary waveguide before the front end of the taper. The secondary waveguide terminates in a ridge with a fixed width w3 of about 50-170 nm that is between the front end of the taper and the air bearing surface (ABS). The ridge enables transverse magnetic (TM) transmission mode efficiency above 90% even with a typical process misalignment in the cross-track and height directions. The primary waveguide has a front section with width w2 between an end of its tapered sides and the ABS where w2 is substantially larger than w3.

Abstract: A TMR (tunneling magnetoresistive) read sensor is formed in which a portion of the sensor stack containing the ferromagnetic free layer and the tunneling barrier layer is patterned to define a narrow trackwidth, but a synthetic antiferromagnetic pinning/pinned layer is left substantially unpatterned and extends in substantially as-deposited form beyond the lateral edges bounding the patterned portion. The narrow trackwidth of the patterned portion permits high resolution for densely recorded data. The larger pinning/pinned layer significantly improves magnetic stability and reduces thermal noise, while the method of formation eliminates possible ion beam etch (IBE) or reactive ion etch (RIE) damage to the edges of the pinning/pinned layer.

Abstract: This document discusses, among other things, an impedance detection circuit, method, and integrated circuit, comprising a ramp-up current generation circuit and an impedance determining circuit, wherein the ramp-up current generation circuit is configured to input a ramp-up current including n breaks to a port of a device where the ramp-up current generation circuit is disposed, to which port an external device is connected, and wherein the impedance determining circuit is configured to detect an impedance of the external device in each break time period of the ramp-up current input by the ramp-up current generation circuit until the impedance of the external device is acquired by detection in the last break time period of the n breaks.

Abstract: A perpendicular recording medium having a perpendicular magnetic recording layer and a magnetically soft underlayer structure disposed beneath the recording layer. The soft underlayer structure includes at least first and second soft magnetic layers having different magnetic permeabilities to create a magnetic permeability gradient in the soft underlayer structure. One or more of the soft magnetic layers can be antiparallel coupled. The soft underlayer structure of the present invention having a magnetic permeability gradient advantageously leads to reduced adjacent track erasure (ATE) while maintaining good overwrite (OW) properties.

Abstract: A two part ion beam etch sequence involving low energy (<300 eV) is disclosed for fabricating a free layer width (FLW) as small as 20-25 nm in a MTJ element. A first etch process has one or more low incident angles and accounts for removal of 70% to 100% of the MTJ stack that is not covered by an overlying photoresist layer. The second etch process employs one or more high incident angles and a sweeping motion that is repeated during a plurality of cycles. Sidewall slope may be adjusted by varying the incident angle during either of the etch processes. FLW is about 30 nm less than an initial critical dimension in the photoresist layer while maintaining a MR ratio over 60% and low RA (resistance×area) value of 1.0 ohm-?m2.

Abstract: A TMR (tunneling magnetoresistive) read sensor is formed in which a portion of the sensor stack containing the ferromagnetic free layer and the tunneling barrier layer is patterned to define a narrow trackwidth, but a synthetic antiferromagnetic pinning/pinned layer is left substantially unpatterned and extends in substantially as-deposited form beyond the lateral edges bounding the patterned portion. The narrow trackwidth of the patterned portion permits high resolution for densely recorded data. The larger pinning/pinned layer significantly improves magnetic stability and reduces thermal noise, while the method of formation eliminates possible ion beam etch (IBE) or reactive ion etch (RIE) damage to the edges of the pinning/pinned layer.

Abstract: A perpendicular magnetic recording (PMR) head is fabricated with a pole tip shielded laterally by a graded side shield that is conformal to the shape of the pole tip at an upper portion of the shield but not conformal to the pole tip at a lower portion. The shield includes a trailing shield, that is conformal to the trailing edge of the pole tip and may include a leading edge shield that magnetically connects two bottom ends of the graded side shield.

Abstract: A two part ion beam etch sequence involving low energy (<300 eV) is disclosed for fabricating a free layer width (FLW) as small as 20-25 nm in a MTJ element. A first etch process has one or more low incident angles and accounts for removal of 70% to 100% of the MTJ stack that is not covered by an overlying photoresist layer. The second etch process employs one or more high incident angles and a sweeping motion that is repeated during a plurality of cycles. Sidewall slope may be adjusted by varying the incident angle during either of the etch processes. FLW is about 30 nm less than an initial critical dimension in the photoresist layer while maintaining a MR ratio over 60% and low RA (resistance×area) value of 1.0 ohm-?m2.

Abstract: A perpendicular magnetic recording (PMR) head is fabricated with a pole tip shielded laterally by a graded side shield that is conformal to the shape of the pole tip at an upper portion of the shield but not conformal to the pole tip at a lower portion. The shield includes a trailing shield, that is conformal to the trailing edge of the pole tip and may include a leading edge shield that magnetically connects two bottom ends of the graded side shield.