Patents by Inventor JIANJIANG ZENG

JIANJIANG ZENG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250013468
    Abstract: Embodiments of this application disclose an instruction translation method. The method includes: obtaining a return instruction of a function call instruction; obtaining a first address mapping result based on a second address indicated in the return instruction; storing the first address mapping result in a running stack space; and obtaining a first translation result of the return instruction, where the first translation result is a binary translation result of the return instruction, and the second translation result indicates to obtain, from a target location, an instruction indicated by the first address mapping result and execute the instruction. In this application, a running stack space of a source program is reused, thereby saving a storage space. In addition, an address of a return instruction does not need to be checked each time the return instruction is translated, thereby reducing overheads during translation and increasing program running efficiency.
    Type: Application
    Filed: September 26, 2024
    Publication date: January 9, 2025
    Inventors: Xianzhe LIU, Jianjiang ZENG, Yandong LV
  • Publication number: 20240419443
    Abstract: Embodiments of this application provide example computing chips and instruction processing method related to the field of integrated circuit technologies. One example computing chip uses a superscalar processor architecture, and includes an instruction processing unit and a plurality of registers that are separately coupled to the instruction processing unit. The plurality of registers include a general purpose register and a plurality of private registers that are separately coupled to the general purpose register. The general purpose register is configured to store an execution result of a microinstruction that is in a plurality of microinstructions of a computing task and that is executed before a jump instruction and whose execution result is referenced by a microinstruction that is executed after the jump instruction. Each private register in the plurality of private registers is configured to store an execution result of any microinstruction in the plurality of microinstructions.
    Type: Application
    Filed: June 12, 2024
    Publication date: December 19, 2024
    Inventors: Ruoyu ZHOU, Wenbo SUN, Jianjiang ZENG, Guozhu LI, Xiping ZHOU, Heng LIAO
  • Publication number: 20240281381
    Abstract: This application discloses a data storage apparatus and a data processing method. The data storage apparatus includes a memory and a first near-data processing NDP unit, the first NDP unit is electrically connected to the memory, and the data storage apparatus is connected to a processor through a bus. The first NDP unit is configured to store first physical address information. The information points to first address space, and the first address space is a section of contiguous memory space that the first NDP unit has permission to use. The memory is configured to store, in the first address space, first data from the processor. The first NDP unit is further configured to read a part or all of the first data from the first address space based on an obtained first offset address and the first physical address information, and perform computation.
    Type: Application
    Filed: February 29, 2024
    Publication date: August 22, 2024
    Applicant: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Han Lin, Yuxuan Chen, JIANJIANG ZENG