Abstract: This application provides a drive and a data transmission method, to implement low-latency transmission. The drive includes a CDR circuit, an elastic buffer, a receiver circuit, and a transmitter circuit. The CDR circuit is configured to recover a receive clock from a received signal. The receiver circuit is configured to recover sent data from the received signal by using the receive clock. The elastic buffer is configured to move the sent data in by using the receive clock and move the data out by using the receive clock. The transmitter circuit is configured to send the sent data from the elastic buffer by using the receive clock.

Abstract: Provided are a mutant HPPD polypeptide having high resistance to a herbicide and an encoding gene thereof, and an application thereof in an improved plant. The amino acid at position 282 of the mutant HPPD polypeptide is mutated from arginine to serine at a wild-type HPPD polypeptide. In addition, the mutant HPPD polypeptide further comprises an amino acid at position 349 that is mutated from glutamic acid to lysine, and/or an amino acid at position 156 that is mutated from alanine to valine. The mutated HPPD polypeptide can be used for cultivating plants having resistance to a herbicide having HPPD inhibition.

Abstract: An eye gaze tracking method, apparatus and system are provided, which belong to the technical field of image processing. The eye gaze tracking method includes: capturing, by at least two cameras, frames of facial images when a viewer views display screen; segmenting a current frame of facial image with pre-trained eye detection model to obtain an image for left and right eyes; calculating a similarity between the current frame of facial image and each of previous N frames of facial images; if the similarity between the current frame of facial image and each of previous N frames of facial images is less than the preset threshold, detecting a position on display screen at which the eyes of the viewer gaze with pre-trained eye detection model. Embodiments of the present disclosure can improve accuracy and efficiency of eye gaze tracking.

Abstract: An eye gaze tracking method, apparatus and system are provided, which belong to the technical field of image processing. The eye gaze tracking method includes: capturing, by at least two cameras, frames of facial images when a viewer views display screen; segmenting a current frame of facial image with pre-trained eye detection model to obtain an image for left and right eyes; calculating a similarity between the current frame of facial image and each of previous N frames of facial images; if the similarity between the current frame of facial image and each of previous N frames of facial images is less than the preset threshold, detecting a position on display screen at which the eyes of the viewer gaze with pre-trained eye detection model. Embodiments of the present disclosure can improve accuracy and efficiency of eye gaze tracking.

Abstract: Embodiments of this application disclose a data interface equalization adjustment method and apparatus, a device, and a storage medium, and relate to the field of data interface technologies. The method includes: A second device determines equalization parameter indication information of a first transmitter TX on a first data interface. The second device sends a first equalization training sequence block ETSB to a corresponding RX on the first data interface through a TX on a second data interface, where the first ETSB carries the equalization parameter indication information and equalization target indication information, and the equalization target indication information indicates that the first TX is an equalization target. The first device determines the equalization target to be the first TX based on the equalization target indication information, and adjusts an equalization parameter of the first TX to an equalization parameter indicated by the equalization parameter indication information.

Abstract: An equalization time configuration method is applied to a processor system in which a Peripheral Component Interconnect Express (PCIe) bus or a Cache Coherent Interconnect for Accelerators (CCIX) bus is used. The equalization time configuration method includes determining a working physical layer (PHY) type of a master chip and a working PHY type of a slave chip, determining an equalization time of the slave chip in a fourth phase of equalization based on the working PHY type of the master chip, and determining an equalization time of the master chip in a third phase of the equalization based on the working PHY type of the slave chip.

Abstract: An electronic assembly includes a first electronic component, a second electronic component, and an electrical connector connecting the first electronic component and the second electronic component. The electrical connector includes a first multilayer circuit board and a terminal that includes a plurality of signal terminals and a plurality of ground terminals. Each signal terminal is electrically connected to a signal interface of the first electronic component and a signal interface of the second electronic component. Signal terminals configured to transmit a same signal form one group of signal terminals, and at least one ground terminal is disposed between two adjacent groups of signal terminals. The first multilayer circuit board includes at least one layer of first ground copper sheet. The first electronic component includes a second multilayer circuit board, and the second multilayer circuit board includes at least one layer of second ground copper sheet.

Abstract: A retimer application system is provided, which includes a primary chip, a retimer, and a secondary chip. After first link training is completed, the retimer is configured to store, in a first storage area, an equalization parameter corresponding to each rate during the first link training, and data stored in the first storage area is not lost when the retimer performs a reset operation. The retimer is further configured to: receive a reset indication, and perform the reset operation according to the reset indication. The primary chip and the secondary chip are configured to perform second link training triggered by the reset indication. During the second link training, the retimer is further configured to: invoke the equalization parameter, and transparently transmit a training sequence in the second link training to the primary chip or the secondary chip based on the equalization parameter.

Abstract: An equalization time configuration method is applied to a processor system in which a Peripheral Component Interconnect Express (PCIe) bus or a Cache Coherent Interconnect for Accelerators (CCIX) bus is used. The equalization time configuration method includes determining a working physical layer (PHY) type of a master chip and a working PHY type of a slave chip, determining an equalization time of the slave chip in a fourth phase of equalization based on the working PHY type of the master chip, and determining an equalization time of the master chip in a third phase of the equalization based on the working PHY type of the slave chip.

Abstract: A controller for data strobe signal (DQS) position adjustment includes, when the controller obtains margin effective widths of all data signals in a transmission bus, it determines a left boundary and a right boundary based on the margin effective widths, where the left boundary is a largest value in minimum values of the margin effective widths of all the DQs, and the right boundary is a smallest value in maximum values of the corresponding margin effective widths when all the DQs are aligned with the left boundary. The controller calculates a first central position based on the left boundary and the right boundary, where the first central position is a center of a smallest margin effective width obtained after all the DQs are aligned during read data training, and adjusts a delay line (DL) of the DQS to the first central position.

Abstract: An equalization time configuration method, applied to a processor system in which a Peripheral Component Interconnect Express (PCIe) bus or a Cache Coherent Interconnect for Accelerators (CCIX) bus is used, includes determining a working physical layer (PHY) type of a master chip and a working PHY type of a slave chip, determining an equalization time of the slave chip in a fourth phase of equalization based on the working PHY type of the master chip, and determining an equalization time of the master chip in a third phase of the equalization based on the working PHY type of the slave chip.

Abstract: This application provides a drive and a data transmission method, to implement low-latency transmission. The drive includes a CDR circuit, an elastic buffer, a receiver circuit, and a transmitter circuit. The CDR circuit is configured to recover a receive clock from a received signal. The receiver circuit is configured to recover sent data from the received signal by using the receive clock. The elastic buffer is configured to move the sent data in by using the receive clock and move the data out by using the receive clock. The transmitter circuit is configured to send the sent data from the elastic buffer by using the receive clock.

Abstract: A retimer application system is provided, which includes a primary chip, a retimer, and a secondary chip. After first link training is completed, the retimer is configured to store, in a first storage area, an equalization parameter corresponding to each rate during the first link training, and data stored in the first storage area is not lost when the retimer performs a reset operation. The retimer is further configured to: receive a reset indication, and perform the reset operation according to the reset indication. The primary chip and the secondary chip are configured to perform second link training triggered by the reset indication. During the second link training, the retimer is further configured to: invoke the equalization parameter, and transparently transmit a training sequence in the second link training to the primary chip or the secondary chip based on the equalization parameter.

Abstract: A retimer is provided. The retimer includes: a data channel circuit, configured to implement, under a function of a current phase locked loop, equalization processing-based transparent transmission of a signal between a first communications device and a second communications device; and the link adjustment circuit, configured to: when determining, based on link status information of the data channel circuit, that a rate of a link needs to be changed, configure an operating parameter of a target phase locked loop as an operating parameter corresponding to a changed rate; and switch the currently used phase locked loop to the target phase locked loop when detecting that the link enters a rate-changing state, where the data channel circuit is further configured to implement, under a function of the target phase locked loop, the transparent transmission of a signal between the first communications device and the second communications device.

Abstract: An equalization time configuration method, applied to a processor system in which a Peripheral Component Interconnect Express (PCIe) bus or a Cache Coherent Interconnect for Accelerators (CCIX) bus is used, includes determining a working physical layer (PHY) type of a master chip and a working PHY type of a slave chip, determining an equalization time of the slave chip in a fourth phase of equalization based on the working PHY type of the master chip, and determining an equalization time of the master chip in a third phase of the equalization based on the working PHY type of the slave chip.

Abstract: A controller for data strobe signal (DQS) position adjustment includes, when the controller obtains margin effective widths of all data signals in a transmission bus, it determines a left boundary and a right boundary based on the margin effective widths, where the left boundary is a largest value in minimum values of the margin effective widths of all the DQs, and the right boundary is a smallest value in maximum values of the corresponding margin effective widths when all the DQs are aligned with the left boundary. The controller calculates a first central position based on the left boundary and the right boundary, where the first central position is a center of a smallest margin effective width obtained after all the DQs are aligned during read data training, and adjusts a delay line (DL) of the DQS to the first central position.

Abstract: A retimer is provided. The retimer includes: a data channel circuit, configured to implement, under a function of a current phase locked loop, equalization processing-based transparent transmission of a signal between a first communications device and a second communications device; and the link adjustment circuit, configured to: when determining, based on link status information of the data channel circuit, that a rate of a link needs to be changed, configure an operating parameter of a target phase locked loop as an operating parameter corresponding to a changed rate; and switch the currently used phase locked loop to the target phase locked loop when detecting that the link enters a rate-changing state, where the data channel circuit is further configured to implement, under a function of the target phase locked loop, the transparent transmission of a signal between the first communications device and the second communications device.